1. Determine and output the factorial of an input number.

<pre class='lang-cpp line-numbers'><code>start
int fact = 1

print “Enter a positive integer: “
input num

if (num==0)
	print “invalid”

elseif (num&lt;0)
	print “NA”

elseif (num&gt;0)
	while (i&lt;=num)
		fact=fact * i
		i++
	endwhile
	print factorial
endif

end</code></pre>

CPE102L

Assignment 1

<p>No code in here since we conducted it on the laboratory. So, I'll just provide the file.</p><a target="_blank" href="https://drive.google.com/file/d/1-fuDlDLhHFxb0Sme7lbqtuSxhyCCLQAj/view?usp=sharing">Click here to download the file</a>

CPE108L

Laboratory Report 1

Data Transmission and Reception through I/O Boards

<p>There is also no code for this one as it was conducted on the laboratory.</p><a href='https://drive.google.com/file/d/1nIwqgQ8X59FD0BJzAphU_J5NqhxW-VlF/view?usp=sharing' target='_blank'>Click here to download the file</a>

Laboratory Report 2

<h5><strong>Part I - Time Delay</strong></h5>
<pre><strong>A. Using LEDs</strong></pre>
<pre class="language-asm6502 line-numbers"><code>ORG 0000H
MAIN:
	CLR A
	MOV A, #06H
	MOV B, #03H
AGAIN:
	DEC A
	DJNZ B, AGAIN
MOV R0, #03H
DJNZ R0, $
ADD A, B
MOV P1, A
END</code></pre>
<br />
<pre>	<strong>B. Using Seven-Segment Display (SSD)</strong></pre>
<pre class="language-asm6502 line-numbers"><code>ORG 0000H
START:
	SETB P3.3
	SETB P3.4
ONE: CALL DELAY
	MOV A, P2
	MOV P1, A
	CALL DELAY
TWO: CLR P3.3
	CALL DELAY
	CLR A
	MOV A, P2
	MOV P1, A
	CALL DELAY
THREE: CLR P3.4
	SETB P3.3
	CALL DELAY
	CLR A
	MOV A, P2
	MOV P1, A
	CALL DELAY
FOUR: CLR P3.3
	CLR P3.4
	CALL DELAY
	CLR A
	MOV A, P2
	MOV P1, A
	CALL DELAY
	JMP START
DELAY: MOV R0, #45H
	DJNZ R0, $
	RET
END</code></pre>
<br />
<h5><strong>Part II - I/O Port Interface with Time Delay</strong></h5>
<pre class="language-asm6502 line-numbers"><code>ORG 0000H
MAIN:
	CLR A
GETIN:
	CALL DELAY
	MOV A, P2
	CPL A
	JZ GETIN
	CPL A
	MOV P1, A
	CALL ROT
ROT:
	RR A
	MOV P1, A
	CALL ROT
DELAY:
	MOV R0, #0FH
L1: MOV R1, #01H
L2: MOV R2, #01H
	DJNZ R2, $
	DJNZ R1, L2
	DJNZ R0, L1
	RET
END
</code></pre>
<br /><br />
<p>Laboratory Report:
<a target="_blank" href="https://drive.google.com/file/d/1-s_r0_3tWPHiGqGUTlQcNffRiKH5cCvJ/view?usp=sharing">
Click here to download the file</a>

</p>

Laboratory Report 3

Liquid Crystal Display Character Generation

<h5><strong>Part I - Basic LCD Control</strong></h5>
<pre><strong>	Step 1</strong></pre>
<pre class="language-asm6502 line-numbers"><code>;save data you wish to display in the RAM
MOV 30H, #&#39;M&#39;
MOV 31H, #&#39;A&#39;
MOV 32H, #&#39;P&#39;
MOV 33H, #&#39;U&#39;
MOV 34H, #&#39;A&#39;
MOV 35H, #0 ;end of data marker

;initializing the display
CLR P1.3;clear pin RS to select register (0-instruction register for write and busy flag: address counter for read) ;indicate that instructions are being sent to the module

;function set
CLR P1.7 ; |
CLR P1.6 ; |
SETB P1.5 ; |
CLR P1.4 ; | high nibble set

SETB P1.2 ; |
CLR P1.2 ; | negative edge on E

CALL delay ; wait for BF to clear
; function set sent for first time - tells module to
; go into 4-bit mode

SETB P1.2 ; |
CLR P1.2 ; | negative edge on E
; same function set high nibble sent a second time
SETB P1.7 ; low nibble set (only P1.7 needed to be changed)
SETB P1.2 ; |

CLR P1.2 ; | negative edge on E
; function set low nibble sent

CALL delay ; wait for BF to clear

; entry mode set
; set to increment with no shift
CLR P1.7 ; |
CLR P1.6 ; |
CLR P1.5 ; |
CLR P1.4 ; | high nibble set
SETB P1.2 ; |
CLR P1.2 ; | negative edge on E
SETB P1.6 ; |
SETB P1.5 ; |low nibble set
SETB P1.2 ; |
CLR P1.2 ; | negative edge on E
CALL delay ; wait for BF to clear

; display on/off control
; the display is turned on, the cursor is turned on and blinking is turned on
CLR P1.7 ; |
CLR P1.6 ; |
CLR P1.5 ; |
CLR P1.4 ; | high nibble set
SETB P1.2 ; |
CLR P1.2 ; | negative edge on E
SETB P1.7 ; |
SETB P1.6 ; |
SETB P1.5 ; |
SETB P1.4 ; | low nibble set
SETB P1.2 ; |
CLR P1.2 ; | negative edge on E
CALL delay ; wait for BF to clear

; send data
SETB P1.3 ; clear RS - indicates that data is being sent to
; module
MOV R1, #30H ; data to be sent to LCD is stored in 8051 RAM,
; starting at location 30H
loop:
	MOV A, @R1 ; move data pointed to by R1 to A
	JZ finish ; if A is 0, then end of data has been reached – jump
; out of loop
CALL sendCharacter ; send data in A to LCD module
INC R1 ; point to next piece of data
JMP loop ; repeat
finish:
	JMP $
sendCharacter:
	MOV C, ACC.7 ; |
	MOV P1.7, C ; |
	MOV C, ACC.6 ; |
	MOV P1.6, C ; |
	MOV C, ACC.5 ; |
	MOV P1.5, C ; |
	MOV C, ACC.4 ; |
	MOV P1.4, C ; | high nibble set
	SETB P1.2 ; |
	CLR P1.2 ; | negative edge on E
	MOV C, ACC.3 ; |
	MOV P1.7, C ; |
	MOV C, ACC.2 ; |
	MOV P1.6, C ; |
	MOV C, ACC.1 ; |
	MOV P1.5, C ; |
	MOV C, ACC.0 ; |
	MOV P1.4, C ; | low nibble set
	SETB P1.2 ; |
	CLR P1.2 ; | negative edge on E
	CALL delay ; wait for BF to clear
delay:
	MOV R0, #200
	DJNZ R0, $
	RET
END</code></pre>
<br />
<pre>	<strong>Step 12-A</strong></pre>
<pre class="language-asm6502 line-numbers"><code>;save data you wish to display in the RAM
MOV 30H, #&#39;A&#39;
MOV 31H, #&#39;N&#39;
MOV 32H, #&#39;O&#39;
MOV 33H, #&#39;N&#39;
MOV 34H, #&#39;Y&#39;
MOV 35H, #&#39;M&#39;
MOV 36H, #&#39;O&#39;
MOV 37H, #&#39;U&#39;
MOV 38H, #&#39;S&#39;
MOV 39H, #&#39;S&#39;
MOV 3AH, #&#39;E&#39;
MOV 3BH, #&#39;C&#39;
MOV 3CH, #&#39;R&#39;
MOV 3DH, #&#39;E&#39;
MOV 3EH, #&#39;T&#39;
MOV 3FH, #0 ;end of data marker

;initializing the display
CLR P1.3;clear pin RS to select register (0-instruction register for write and busy flag: address counter for read) ;indicate that instructions are being sent to the module

;function set
CLR P1.7 ; |
CLR P1.6 ; |
SETB P1.5 ; |
CLR P1.4 ; | high nibble set

SETB P1.2 ; |
CLR P1.2 ; | negative edge on E

CALL delay ; wait for BF to clear
; function set sent for first time - tells module to
; go into 4-bit mode

SETB P1.2 ; |
CLR P1.2 ; | negative edge on E
; same function set high nibble sent a second time
SETB P1.7 ; low nibble set (only P1.7 needed to be changed)
SETB P1.2 ; |

CLR P1.2 ; | negative edge on E
; function set low nibble sent

CALL delay ; wait for BF to clear

; entry mode set
; set to increment with no shift
CLR P1.7 ; |
CLR P1.6 ; |
CLR P1.5 ; |
CLR P1.4 ; | high nibble set
SETB P1.2 ; |
CLR P1.2 ; | negative edge on E
SETB P1.6 ; |
SETB P1.5 ; |low nibble set
SETB P1.2 ; |
CLR P1.2 ; | negative edge on E
CALL delay ; wait for BF to clear

; display on/off control
; the display is turned on, the cursor is turned on and blinking is turned on
CLR P1.7 ; |
CLR P1.6 ; |
CLR P1.5 ; |
CLR P1.4 ; | high nibble set
SETB P1.2 ; |
CLR P1.2 ; | negative edge on E
SETB P1.7 ; |
SETB P1.6 ; |
SETB P1.5 ; |
SETB P1.4 ; | low nibble set
SETB P1.2 ; |
CLR P1.2 ; | negative edge on E
CALL delay ; wait for BF to clear

; send data
SETB P1.3 ; clear RS - indicates that data is being sent to
; module
MOV R1, #30H ; data to be sent to LCD is stored in 8051 RAM,
; starting at location 30H
loop:
	MOV A, @R1 ; move data pointed to by R1 to A
	JZ finish ; if A is 0, then end of data has been reached – jump
; out of loop
CALL sendCharacter ; send data in A to LCD module
INC R1 ; point to next piece of data
JMP loop ; repeat
finish:
	JMP $
sendCharacter:
	MOV C, ACC.7 ; |
	MOV P1.7, C ; |
	MOV C, ACC.6 ; |
	MOV P1.6, C ; |
	MOV C, ACC.5 ; |
	MOV P1.5, C ; |
	MOV C, ACC.4 ; |
	MOV P1.4, C ; | high nibble set
	SETB P1.2 ; |
	CLR P1.2 ; | negative edge on E
	MOV C, ACC.3 ; |
	MOV P1.7, C ; |
	MOV C, ACC.2 ; |
	MOV P1.6, C ; |
	MOV C, ACC.1 ; |
	MOV P1.5, C ; |
	MOV C, ACC.0 ; |
	MOV P1.4, C ; | low nibble set
	SETB P1.2 ; |
	CLR P1.2 ; | negative edge on E
	CALL delay ; wait for BF to clear
delay:
	MOV R0, #200
	DJNZ R0, $
	RET
END
</code></pre>
<br />
<pre>	<strong>Step 12-B</strong></pre>
<pre class="language-asm6502 line-numbers"><code>;save data you wish to display in the RAM
MOV 30H, #&#39;A&#39;
MOV 31H, #&#39;N&#39;
MOV 32H, #&#39;O&#39;
MOV 33H, #&#39;N&#39;
MOV 34H, #&#39;Y&#39;
MOV 35H, #&#39;M&#39;
MOV 36H, #&#39;O&#39;
MOV 37H, #&#39;U&#39;
MOV 38H, #&#39;S&#39;
MOV 39H, #&#39;S&#39;
MOV 3AH, #&#39;E&#39;
MOV 3BH, #&#39;C&#39;
MOV 3CH, #&#39;R&#39;
MOV 3DH, #&#39;E&#39;
MOV 3EH, #&#39;T&#39;
MOV 3FH, #0 ;end of data marker

;initializing the display
CLR P1.3;clear pin RS to select register (0-instruction register for write and busy flag: address counter for read) ;indicate that instructions are being sent to the module

;function set
CLR P1.7 ; |
CLR P1.6 ; |
SETB P1.5 ; |
CLR P1.4 ; | high nibble set

SETB P1.2 ; |
CLR P1.2 ; | negative edge on E

CALL delay ; wait for BF to clear
; function set sent for first time - tells module to
; go into 4-bit mode

SETB P1.2 ; |
CLR P1.2 ; | negative edge on E
; same function set high nibble sent a second time
SETB P1.7 ; low nibble set (only P1.7 needed to be changed)
SETB P1.2 ; |

CLR P1.2 ; | negative edge on E
; function set low nibble sent

CALL delay ; wait for BF to clear

; entry mode set
; set to increment with no shift
CLR P1.7 ; |
CLR P1.6 ; |
CLR P1.5 ; |
CLR P1.4 ; | high nibble set
SETB P1.2 ; |
CLR P1.2 ; | negative edge on E
SETB P1.6 ; |
SETB P1.5 ; |low nibble set
SETB P1.2 ; |
CLR P1.2 ; | negative edge on E
CALL delay ; wait for BF to clear

; display on/off control
; the display is turned on, the cursor is turned on and blinking is turned on
CLR P1.7 ; |
CLR P1.6 ; |
CLR P1.5 ; |
CLR P1.4 ; | high nibble set
SETB P1.2 ; |
CLR P1.2 ; | negative edge on E
SETB P1.7 ; |
SETB P1.6 ; |
SETB P1.5 ; |
SETB P1.4 ; | low nibble set
SETB P1.2 ; |
CLR P1.2 ; | negative edge on E
CALL delay ; wait for BF to clear

; send data
SETB P1.3 ; clear RS - indicates that data is being sent to
; module
MOV R1, #30H ; data to be sent to LCD is stored in 8051 RAM,
; starting at location 30H
loop:
	MOV A, @R1 ; move data pointed to by R1 to A
	JZ finish ; if A is 0, then end of data has been reached – jump
; out of loop
CALL sendCharacter ; send data in A to LCD module
INC R1 ; point to next piece of data
JMP loop ; repeat
finish:
	JMP $
sendCharacter:
	MOV C, ACC.7 ; |
	MOV P1.7, C ; |
	MOV C, ACC.6 ; |
	MOV P1.6, C ; |
	MOV C, ACC.5 ; |
	MOV P1.5, C ; |
	MOV C, ACC.4 ; |
	MOV P1.4, C ; | high nibble set
	SETB P1.2 ; |
	CLR P1.2 ; | negative edge on E
	MOV C, ACC.3 ; |
	MOV P1.7, C ; |
	MOV C, ACC.2 ; |
	MOV P1.6, C ; |
	MOV C, ACC.1 ; |
	MOV P1.5, C ; |
	MOV C, ACC.0 ; |
	MOV P1.4, C ; | low nibble set
	SETB P1.2 ; |
	CLR P1.2 ; | negative edge on E
	CALL delay ; wait for BF to clear
delay:
	MOV R0, #0FFFFH
	DJNZ R0, $
	RET
END</code></pre>
<br />
<h5><strong>Part II - LCD Character Display</strong></h5>
<pre><strong>	Step 1</strong></pre>
<pre class="language-asm6502 line-numbers"><code>;save data you wish to display in the RAM
MOV 30H, #&#39;A&#39;
MOV 31H, #&#39;N&#39;
MOV 32H, #&#39;O&#39;
MOV 33H, #&#39;N&#39;
MOV 34H, #&#39;Y&#39;
MOV 35H, #&#39;M&#39;
MOV 36H, #&#39;O&#39;
MOV 37H, #&#39;U&#39;
MOV 38H, #&#39;S&#39;
MOV 39H, #&#39;S&#39;
MOV 3AH, #&#39;E&#39;
MOV 3BH, #&#39;C&#39;
MOV 3CH, #&#39;R&#39;
MOV 3DH, #&#39;E&#39;
MOV 3EH, #&#39;T&#39;
MOV 2FH, #0 ;end of data marker

;initializing the display
CLR P1.3;clear pin RS to select register (0-instruction register for write and busy flag: address counter for read) ;indicate that instructions are being sent to the module

;function set
CLR P1.7 ; |
CLR P1.6 ; |
SETB P1.5 ; |
CLR P1.4 ; | high nibble set

SETB P1.2 ; |
CLR P1.2 ; | negative edge on E

CALL delay ; wait for BF to clear
; function set sent for first time - tells module to
; go into 4-bit mode

SETB P1.2 ; |
CLR P1.2 ; | negative edge on E
; same function set high nibble sent a second time
SETB P1.7 ; low nibble set (only P1.7 needed to be changed)
SETB P1.2 ; |

CLR P1.2 ; | negative edge on E
; function set low nibble sent

CALL delay ; wait for BF to clear

; entry mode set
; set to increment with no shift
CLR P1.7 ; |
CLR P1.6 ; |
CLR P1.5 ; |
CLR P1.4 ; | high nibble set
SETB P1.2 ; |
CLR P1.2 ; | negative edge on E
SETB P1.6 ; |
SETB P1.5 ; |low nibble set
SETB P1.2 ; |
CLR P1.2 ; | negative edge on E
CALL delay ; wait for BF to clear

; display on/off control
; the display is turned on, the cursor is turned on and blinking is turned on
CLR P1.7 ; |
CLR P1.6 ; |
CLR P1.5 ; |
CLR P1.4 ; | high nibble set
SETB P1.2 ; |
CLR P1.2 ; | negative edge on E
SETB P1.7 ; |
SETB P1.6 ; |
SETB P1.5 ; |
SETB P1.4 ; | low nibble set
SETB P1.2 ; |
CLR P1.2 ; | negative edge on E
CALL delay ; wait for BF to clear

; send data
SETB P1.3 ; clear RS - indicates that data is being sent to
; module
MOV R1, #3EH ; data to be sent to LCD is stored in 8051 RAM,
; starting at location 30H
loop:
	MOV A, @R1 ; move data pointed to by R1 to A
	JZ finish ; if A is 0, then end of data has been reached – jump
; out of loop
CALL sendCharacter ; send data in A to LCD module
DEC R1 ; point to next piece of data
JMP loop ; repeat
finish:
	JMP $
sendCharacter:
	MOV C, ACC.7 ; |
	MOV P1.7, C ; |
	MOV C, ACC.6 ; |
	MOV P1.6, C ; |
	MOV C, ACC.5 ; |
	MOV P1.5, C ; |
	MOV C, ACC.4 ; |
	MOV P1.4, C ; | high nibble set
	SETB P1.2 ; |
	CLR P1.2 ; | negative edge on E
	MOV C, ACC.3 ; |
	MOV P1.7, C ; |
	MOV C, ACC.2 ; |
	MOV P1.6, C ; |
	MOV C, ACC.1 ; |
	MOV P1.5, C ; |
	MOV C, ACC.0 ; |
	MOV P1.4, C ; | low nibble set
	SETB P1.2 ; |
	CLR P1.2 ; | negative edge on E
	CALL delay ; wait for BF to clear
delay:
	MOV R0, #0FFFFH
	DJNZ R0, $
	RET
END</code></pre>
<br />
<pre><strong>	Step 1</strong></pre>
<pre class="language-asm6502 line-numbers"><code>;save data you wish to display in the RAM
MOV 30H, #&#39;A&#39;
MOV 31H, #&#39;N&#39;
MOV 32H, #&#39;O&#39;
MOV 33H, #&#39;N&#39;
MOV 34H, #&#39;Y&#39;
MOV 35H, #&#39;M&#39;
MOV 36H, #&#39;O&#39;
MOV 37H, #&#39;U&#39;
MOV 38H, #&#39;S&#39;
MOV 39H, #&#39;S&#39;
MOV 3AH, #&#39;E&#39;
MOV 3BH, #&#39;C&#39;
MOV 3CH, #&#39;R&#39;
MOV 3DH, #&#39;E&#39;
MOV 3EH, #&#39;T&#39;
MOV 2FH, #0 ;end of data marker

;initializing the display
CLR P1.3;clear pin RS to select register (0-instruction register for write and busy flag: address counter for read) ;indicate that instructions are being sent to the module

;function set
CLR P1.7 ; |
CLR P1.6 ; |
SETB P1.5 ; |
CLR P1.4 ; | high nibble set

SETB P1.2 ; |
CLR P1.2 ; | negative edge on E

CALL delay ; wait for BF to clear
; function set sent for first time - tells module to
; go into 4-bit mode

SETB P1.2 ; |
CLR P1.2 ; | negative edge on E
; same function set high nibble sent a second time
SETB P1.7 ; low nibble set (only P1.7 needed to be changed)
SETB P1.2 ; |

CLR P1.2 ; | negative edge on E
; function set low nibble sent

CALL delay ; wait for BF to clear

; entry mode set
; set to increment with no shift
CLR P1.7 ; |
CLR P1.6 ; |
CLR P1.5 ; |
CLR P1.4 ; | high nibble set
SETB P1.2 ; |
CLR P1.2 ; | negative edge on E
SETB P1.6 ; |
SETB P1.5 ; |low nibble set
SETB P1.2 ; |
CLR P1.2 ; | negative edge on E
CALL delay ; wait for BF to clear

; display on/off control
; the display is turned on, the cursor is turned on and blinking is turned on
CLR P1.7 ; |
CLR P1.6 ; |
CLR P1.5 ; |
CLR P1.4 ; | high nibble set
SETB P1.2 ; |
CLR P1.2 ; | negative edge on E
SETB P1.7 ; |
SETB P1.6 ; |
SETB P1.5 ; |
SETB P1.4 ; | low nibble set
SETB P1.2 ; |
CLR P1.2 ; | negative edge on E
CALL delay ; wait for BF to clear

; send data
SETB P1.3 ; clear RS - indicates that data is being sent to
; module
MOV R1, #3EH ; data to be sent to LCD is stored in 8051 RAM,
; starting at location 30H
loop:
	MOV A, @R1 ; move data pointed to by R1 to A
	JZ finish ; if A is 0, then end of data has been reached – jump
; out of loop
	CALL sendCharacter ; send data in A to LCD module
	DEC R1 ; point to next piece of data
JMP loop ; repeat
finish:
	JMP $
sendCharacter:
	MOV C, ACC.7 ; |
	MOV P1.7, C ; |
	MOV C, ACC.6 ; |
	MOV P1.6, C ; |
	MOV C, ACC.5 ; |
	MOV P1.5, C ; |
	MOV C, ACC.4 ; |
	MOV P1.4, C ; | high nibble set
	SETB P1.2 ; |
	CLR P1.2 ; | negative edge on E
	MOV C, ACC.3 ; |
	MOV P1.7, C ; |
	MOV C, ACC.2 ; |
	MOV P1.6, C ; |
	MOV C, ACC.1 ; |
	MOV P1.5, C ; |
	MOV C, ACC.0 ; |
	MOV P1.4, C ; | low nibble set
	SETB P1.2 ; |
	CLR P1.2 ; | negative edge on E
	CALL delay ; wait for BF to clear
delay:
	MOV R0, #50
	DJNZ R0, $
	RET
END</code></pre>
<br /><br />
<p>Laboratory Report:
<a target="_blank" href="https://drive.google.com/file/d/1-s_r0_3tWPHiGqGUTlQcNffRiKH5cCvJ/view?usp=sharing">
Click here to download the file
</a>
</p>

Laboratory Report 4

<h5><strong>Part 1 - Keypad Scanning</strong></h5>
<pre class="line-numbers"><code class="lang-nasm">start:
	MOV R0, #0 ; clear R0 - the first key is key0
; scan row0
	SETB P0.3 ; set row3
	CLR P0.0 ; clear row0
	CALL colScan ; call column-scan subroutine
	JB F0, finish ; | if F0 is set, jump to end of program
		; | (because the pressed key was found and its number
		; is in R0)

; scan row1
	SETB P0.0 ; set row0
	CLR P0.1 ; clear row1
	CALL colScan ; call column-scan subroutine
	JB F0, finish ; | if F0 is set, jump to end of program
		; | (because the pressed key was found and its number
		; is in R0)

; scan row2
	SETB P0.1 ; set row1
	CLR P0.2 ; clear row2
	CALL colScan ; call column-scan subroutine
	JB F0, finish ; | if F0 is set, jump to end of program
		; | (because the pressed key was found and its number
		; is in R0)

; scan row3
	SETB P0.2 ; set row2
	CLR P0.3 ; clear row3
	CALL colScan ; call column-scan subroutine
	JB F0, finish ; | if F0 is set, jump to end of program
		; | (because the pressed key was found and its number
		; is in R0)
	JMP start ; | go back to scan row 0
		; | (this is why row3 is set at the start of the
		; program
		; | - when the program jumps back to start, row3 has
		; just been scanned)

finish:
	JMP $ ; program execution arrives here when key is found – do
		; nothing

; column-scan subroutine
colScan:
	JNB P0.4, gotKey ; if col0 is cleared - key found
	INC R0 ; otherwise move to next key
	JNB P0.5, gotKey ; if col1 is cleared - key found
	INC R0 ; otherwise move to next key
	JNB P0.6, gotKey ; if col2 is cleared - key found
	INC R0 ; otherwise move to next key
	RET ; return from subroutine - key not found
gotKey:
	SETB F0 ; key found - set F0
	RET ; and return from subroutine</code></pre>
<br /><br />
<h5><strong>Part 2 - Data Transmission through Keypad</strong></h5>
<pre class="line-numbers"><code class="lang-nasm">start:
	MOV R0, #0 ; clear R0 - the first key is key0
; scan row0
	SETB P0.3 ; set row3
	CLR P0.0 ; clear row0
	CALL colScan ; call column-scan subroutine
	JB F0, finish ; | if F0 is set, jump to end of program
		; | (because the pressed key was found and its number
		; is in R0)

; scan row1
	SETB P0.0 ; set row0
	CLR P0.1 ; clear row1
	CALL colScan ; call column-scan subroutine
	JB F0, finish ; | if F0 is set, jump to end of program
		; | (because the pressed key was found and its number
		; is in R0)

; scan row2
	SETB P0.1 ; set row1
	CLR P0.2 ; clear row2
	CALL colScan ; call column-scan subroutine
	JB F0, finish ; | if F0 is set, jump to end of program
		; | (because the pressed key was found and its number
		; is in R0)

; scan row3
	SETB P0.2 ; set row2
	CLR P0.3 ; clear row3
	CALL colScan ; call column-scan subroutine
	JB F0, finish ; | if F0 is set, jump to end of program
		; | (because the pressed key was found and its number
		; is in R0)
	JMP start ; | go back to scan row 0
		; | (this is why row3 is set at the start of the
		; program
		; | - when the program jumps back to start, row3 has
		; just been scanned)

finish:
	JMP start ; program execution arrives here when key is found – do
		; nothing

; column-scan subroutine
colScan:
	JNB P0.4, gotKey ; if col0 is cleared - key found
	INC R0 ; otherwise move to next key
	JNB P0.5, gotKey ; if col1 is cleared - key found
	INC R0 ; otherwise move to next key
	JNB P0.6, gotKey ; if col2 is cleared - key found
	INC R0 ; otherwise move to next key
	RET ; return from subroutine - key not found
gotKey:
	SETB F0 ; key found - set F0
	MOV A, R0
	MOV P1, A
	MOV R0, #0
	CLR F0
	RET ; and return from subroutine</code></pre>
<br /><br />
<p>Laboratory Report:  <a href="https://drive.google.com/file/d/1_iSsjTrZg3tyeCahLOehB4CJzZVZf9D-/view?usp=sharing" target="_blank">Click here to download the file</a></p>

Laboratory Report 5

<h5><strong>Basic DC Motor Control</strong></h5>
<pre class="line-numbers"><code class="lang-nasm">MOV TMOD, #50H ; put timer 1 in event counting mode
SETB TR1 ; start timer 1
MOV DPL, #LOW(LEDcodes) ; | put the low byte of the start address of
	; the
	; | 7-segment code table into DPL

MOV DPH, #HIGH(LEDcodes) ; put the high byte into DPH

CLR P3.4 ; |
CLR P3.3 ; | enable Display 0

again:
	CALL setDirection ; set the motor's direction
	MOV A, TL1 ; move timer 1 low byte to A
	CJNE A, #10, skip ; if the number of revolutions is not 10 skip
		; next instruction
	CALL clearTimer ; if the number of revolutions is 10, reset
		; timer 1

skip:
	MOVC A, @A+DPTR ; | get 7-segment code from code table - the
		; index into the table is
		; | decided by the value in A
		; | (example: the data pointer points to the
		; start of the
		; | table - if there are two revolutions, then
		; A will contain two,
		; | therefore the second code in the table
		; will be copied to A)
	MOV C, F0 ; move motor direction value to the carry
	MOV ACC.7, C ; and from there to ACC.7 (this will ensure
		; Display 0's decimal point
		; will indicate the motor's direction)
	MOV P1, A ; | move (7-seg code for) number of
		; revolutions and motor direction
		; | indicator to Display 0
	JMP again ; do it all again

setDirection:
	PUSH ACC ; save value of A on stack
	PUSH 20H ; save value of location 20H (first bit-
		; addressable
		; location in RAM) on stack
	CLR A ; clear A
	MOV 20H, #0 ; clear location 20H
	MOV C, P2.0 ; put SW0 value in carry
	MOV ACC.0, C ; then move to ACC.0
	MOV C, F0 ; move current motor direction in carry
	MOV 0, C ; and move to LSB of location 20H (which has
		; bit address 0)
	CJNE A, 20H, changeDir ; | compare SW0 (LSB of A) with F0 (LSB of
		; 20H)
		; | - if they are not the same, the motor's
		; direction needs to be reversed
	JMP finish ; if they are the same, motor's direction does
		; not need to be changed

changeDir:
	CLR P3.0 ; |
	CLR P3.1 ; | stop motor
	CALL clearTimer ; reset timer 1 (revolution count restarts
		; when motor direction changes)
	MOV C, P2.0 ; move SW0 value to carry
	MOV F0, C ; and then to F0 - this is the new motor
		; direction
	MOV P3.0, C ; move SW0 value (in carry) to motor control
		; bit 1
	CPL C ; invert the carry
	MOV P3.1, C ; | and move it to motor control bit 0 (it
		; will therefore have the opposite
		; | value to control bit 1 and the motor willfinish:

finish:
	POP 20H ; get original value for location 20H from the
		; stack
	POP ACC ; get original value for A from the stack
	RET ; return from subroutine
clearTimer:
	CLR A ; reset revolution count in A to zero
	CLR TR1 ; stop timer 1
	MOV TL1, #0 ; reset timer 1 low byte to zero
	SETB TR1 ; start timer 1
	RET ; return from subroutine
		; | this label points to the start address of the 7-segment code table which is
		; | stored in program memory using the DB command below

LEDcodes:

DB 11000000B, 11111001B, 10100100B, 10110000B, 10011001B, 10010010B, 10000010B, 11111000B, 10000000B, 10010000B
</code></pre>
<br /><br />
<p>Laboratory Report:  <a href="https://drive.google.com/file/d/1nRJcpFSxAwXqzW6apU8amXsVWqG49vYt/view?usp=sharing" target="_blank">Click here to download the file</a></p>

Laboratory Report 6

<h5>Excess 5 to Binary Coded Decimal</h5>
<p><i>This Project was made using EdSim51DI like the other Laboratory Experiments. You may download the tool in their <a href="https://www.edsim51.com/8051simulator/edsim51di.zip" target="_blank">site here</a>.</i></p>
<br />
<p>The setup of the project is different from the default. So first, we need to setup the Dynamic Interface of the EdSim51DI by clicking the DI button located near the LEDs.</p><br />
<p>This will be the default settings of the EdSim51DI.</p>
<img src="https://i.imgur.com/lSNlI4K.png" alt="Default settings" class="img-fluid" />
<br /><br />
<p>This will be the new settings of the EdSim51DI.</p>
<img src="https://i.imgur.com/eVzbu3n.png" alt="New settings" class="img-fluid" />
<br /><br /><br />
<h5><strong>Code:</strong></h5>
<pre class="line-numbers"><code class="lang-nasm">;Excess-5 to BCD
ORG 0000H	;Initialize start address

MAIN:
CALL CLEAR	;call label to clear registers

;set seven-segment display (SSD)
MOV 30H, #11000000B 	;store 0 to display in SSD
MOV 31H, #11111001B 	;store 1 to display in SSD
MOV 32H, #10100100B 	;store 2 to display in SSD
MOV 33H, #10110000B 	;store 3 to display in SSD
MOV 34H, #10011001B 	;store 4 to display in SSD
MOV 35H, #10010010B 	;store 5 to display in SSD
MOV 36H, #10000010B 	;store 6 to display in SSD
MOV 37H, #11111000B 	;store 7 to display in SSD
MOV 38H, #10000000B 	;store 8 to display in SSD
MOV 39H, #10010000B		;store 9 to display in SSD

;set Liquid Crystal Display (LCD) to display 'ERROR'
MOV 3AH, #'E'	;store E to display in LCD
MOV 3BH, #'R'	;store R to display in LCD
MOV 3CH, #'R'	;store R to display in LCD
MOV 3DH, #'O'	;store O to display in LCD
MOV 3EH, #'R'	;store R to display in LCD
MOV 3FH, #0		;end of data

READINP:
	CALL DELAY		;time delay
	CALL CLEAR		;clear the registers
	MOV A, P2		;store input from switches into register A
	CPL A			;inverts the content of register A
	
	
	
	CALL SUB5		;call SUB5 to subtract 5 from the input
	CALL CHECK		;call check to validate input

OUTLED: ;Output to LEDs
	CALL CLEARLCD	;clear display on LCD
	CPL A			;inverts the content of register A
	MOV B, A		;store contents of reg B to reg B
	MOV P1, B		;display the content of B into the LEDs
	
	JMP READINP		;Detect input again

SUB5: ;Subtract 5 from input
	MOV R0, #05		;sets R0 to 5

SUBLOOP:	;loop for subtraction
	DEC A				;Decrement 1 from reg A
	DJNZ R0, SUBLOOP	;Loop 5 times to subtract 5 from A
	RET

CHECK: ;CHECK input if within BCD range (0-9 in Decimal)
C9:
	CJNE A, #09H, C8	;continue to next line if reg A == #09H, else, jump to C8
	MOV P3, 39H			;Display '9' (stored in 39H) on the SSD
	RET
C8:
	CJNE A, #08H, C7	;continue to next line if reg A == #08H, else, jump to C7
	MOV P3, 38H			;Display '8' (stored in 39H) on the SSD
	RET
C7:
	CJNE A, #07H, C6	;continue to next line if reg A == #07H, else, jump to C6
	MOV P3, 37H			;Display '7' (stored in 39H) on the SSD
	RET
C6:
	CJNE A, #06H, C5	;continue to next line if reg A == #06H, else, jump to C5
	MOV P3, 36H			;Display '6' (stored in 39H) on the SSD
	RET
C5:
	CJNE A, #05H, C4	;continue to next line if reg A == #05H, else, jump to C4
	MOV P3, 35H			;Display '5' (stored in 39H) on the SSD
	RET
C4:
	CJNE A, #04H, C3	;continue to next line if reg A == #04H, else, jump to C3
	MOV P3, 34H			;Display '4' (stored in 39H) on the SSD
	RET
C3:
	CJNE A, #03H, C2	;continue to next line if reg A == #03H, else, jump to C2
	MOV P3, 33H			;Display '3' (stored in 39H) on the SSD
	RET
C2:
	CJNE A, #02H, C1	;continue to next line if reg A == #02H, else, jump to C1
	MOV P3, 32H			;Display '2' (stored in 39H) on the SSD
	RET
C1:
	CJNE A, #01H, C0	;continue to next line if reg A == #01H, else, jump to C0
	MOV P3, 31H			;Display '1' (stored in 39H) on the SSD
	RET
C0:
	CJNE A, #00H, LCD		;continue to next line if reg A == #09H, else, jump to LCD
	MOV P3, 30H				;Display '0' (stored in 39H) on the SSD
	RET

LCD: ;Display "ERROR" on LCD

; initialise the display
; see instruction set for details
CLR P1.3		; clear RS - indicates that instructions are being sent to the module
; function set	
	CLR P1.7		; |
	CLR P1.6		; |
	SETB P1.5		; |
	CLR P1.4		; | high nibble set

	SETB P1.2		; |
	CLR P1.2		; | negative edge on E

	CALL DELAY		; wait for BF to clear	
; function set sent for first time - tells module to go into 4-bit mode

	SETB P1.2		; |
	CLR P1.2		; | negative edge on E
; same function set high nibble sent a second time

	SETB P1.7		; low nibble set (only P1.7 needed to be changed)
	SETB P1.2		; |
	CLR P1.2		; | negative edge on E

; function set low nibble sent
	CALL DELAY		; wait for BF to clear


; entry mode set
; set to increment with no shift
	CLR P1.7		; |
	CLR P1.6		; |
	CLR P1.5		; |
	CLR P1.4		; | high nibble set

	SETB P1.2		; |
	CLR P1.2		; | negative edge on E

	SETB P1.6		; |
	SETB P1.5		; |low nibble set

	SETB P1.2		; |
	CLR P1.2		; | negative edge on E

	CALL DELAY		; wait for BF to clear


; display on/off control
; the display is turned on, the cursor is turned on and blinking is turned on
	CLR P1.7		; |
	CLR P1.6		; |
	CLR P1.5		; |
	CLR P1.4		; | high nibble set

	SETB P1.2		; |
	CLR P1.2		; | negative edge on E

	SETB P1.7		; |
	SETB P1.6		; |
	SETB P1.5		; |
	SETB P1.4		; | low nibble set

	SETB P1.2		; |
	CLR P1.2		; | negative edge on E

	CALL DELAY		; wait for BF to clear


; send data
	SETB P1.3		; clear RS - indicates that data is being sent to module
	MOV R1, #3AH	; data to be sent to LCD is stored in 8051 RAM, starting at location 3AH
LOOP:
	MOV A, @R1		; move data pointed to by R1 to A
	JZ FINISH		; if A is 0, then end of data has been reached - jump out of loop
	CALL SENDCHAR	; send data in A to LCD module
	INC R1			; point to next piece of data
	JMP LOOP		; repeat

FINISH:
	JMP READINP

SENDCHAR:
	MOV C, ACC.7		; |
	MOV P1.7, C			; |
	MOV C, ACC.6		; |
	MOV P1.6, C			; |
	MOV C, ACC.5		; |
	MOV P1.5, C			; |
	MOV C, ACC.4		; |
	MOV P1.4, C			; | high nibble set

	SETB P1.2			; |
	CLR P1.2			; | negative edge on E

	MOV C, ACC.3		; |
	MOV P1.7, C			; |
	MOV C, ACC.2		; |
	MOV P1.6, C			; |
	MOV C, ACC.1		; |
	MOV P1.5, C			; |
	MOV C, ACC.0		; |
	MOV P1.4, C			; | low nibble set

	SETB P1.2			; |
	CLR P1.2			; | negative edge on E
	
	MOV R0, #50
	CALL DELAY			; wait for BF to clear



CLEAR: ;set registers to zero
	SETB P0.3		; | enable display 3
	SETB P0.4		; | of SSD (leftmost)

	MOV A, #0H		;clear content of reg A
	MOV B, #0H		;clear content of reg B
	MOV R0, #0H		;clear content of R0
	RET

CLEARLCD:
	MOV P1, #00H	;clear display of LCD
	RET

DELAY:
	MOV R0, #50H		;set delay to 50H
	DJNZ R0, $			;While R0 != 0, subtract 1 from R0
	RET

ENDOFCODE:
	END</code></pre>
<br /><br />
<p>Documentation:  <a href="https://drive.google.com/file/d/1T6_OLD1FA4qTcQRUIhR_4I1ZbAFRHe0e/view?usp=sharing" target="_blank">Click here to download the file</a></p>

Design of Experiment

Make a simple calculator using Python about temperature conversion.

<h5>Code: </h5>
<pre class="line-numbers"><code class="lang-python">def CtoF(value):
    F = value*(9/5)+32
    return str(value) + "°C is " + str(F) + "°F"
def FtoC(value):
    C = (value-32)*5/9
    return str(value) + "°F is " + str(C) + "°C"

choice = input("1 - Celsius to Fahrenheit\n2 - Fahrenheit to Celsius\nChoose an option: ")

if int(choice) == 1:
    value = input("Enter value in Celsius: ")
    print(CtoF(float(value)))
elif int(choice) == 2:
    value = input("Enter value in Fahreneheit: ")
    print(FtoC(float(value)))
</code></pre>

DS100-1

Machine Problem 1-1

Create a Python program that displays the Fibonacci sequence up to 20 values. The program should contain loop and def functions.

<h5>Code: </h5>
<pre class="line-numbers"><code class="lang-python">def fib(value):
    previous=0
    result=0
    current=1
    ls = [previous, current]
    
    for i in range(value-2):
        result = current + previous
        previous = current
        current = result
        ls.append(result)
    
    return ls

print("The first 20 Fibonacci numbers are: " + str(fib(20)))</code></pre>

Machine Problem 1-2

Create a Python program for displaying the square of numbers from 0 - 30.

<h5>Code: </h5>
<pre class="line-numbers"><code class="lang-python">def sqr(value):
    sq = []
    
    for i in range(value+1):
        current = i
        sq.append(current**2)
    
    return sq

print("The square of first 30 numbers are: " + str(sqr(30)))
</code></pre>

Machine Problem 1-3

Something about data visualization using matplotlib.

<p>This requires <a href="https://drive.google.com/file/d/1PSP8xvCYD7BVNWsGxdLVVCj3m-KWNZq3/view?usp=sharing" target="_blank">class_grades.csv</a> file in the same directory of the code.</p>
<h5>Code: </h5>
<pre class="line-numbers"><code class="lang-python">import pandas as pd

#importing csv file
data = pd.read_csv('class_grades.csv')
#print(data)

#getting row with index of 4
data = data.iloc[5]
#print(data)

#convertion of pandas dataframe to numpy array
arr1 = data.to_numpy()[1:6]
arr = arr1.astype(np.float64)

name = data.to_numpy()[0]

#print(arr)

import matplotlib.pyplot as plt
%matplotlib inline

x = [1,2,3,4,5]

import numpy as np
model = np.polyfit(x,arr,1)

predict = np.poly1d(model)

x_lin_reg = range(1,6)
y_lin_reg = predict(x_lin_reg) 

plt.scatter(x, arr, c='black')
plt.plot(x_lin_reg, y_lin_reg, c='r')
plt.ylim(1,5)
plt.ylim(0,100)
plt.title(name + " " + str(arr1))

pc = np.corrcoef(x, arr)[0, 1]
print("Pearson coefficient = %s" % str(pc))
</code></pre>

Machine Problem 2

Complete the missing lines in the given code to be able run it without any errors.

<p>This code requires machine-problem-3-data.txt</p>
<h5>Code: </h5>
<pre class="line-numbers"><code class="lang-python">#Insert missing lines here 
import pandas as pd
import numpy as np
import matplotlib.pyplot as plt
from sklearn.linear_model import LinearRegression
%matplotlib inline

data = pd.read_csv('machine-problem-3-data.txt', names = ['Population','Profit'])
#print(data)

cols = data.shape[1]
X = data.iloc[:,0:cols-1]
y = data.iloc[:,cols-1:cols]

X = np.matrix(X.values)
y = np.matrix(y.values)
#print(y.shape,x.shape)

#Insert missing lines here
model = LinearRegression()

model.fit(X, y)

x = np.array(X[:, 0].A1)
f = model.predict(X).flatten()

fig, ax = plt.subplots(figsize=(12,8))
ax.plot(x, f, 'g', label='Prediction')
ax.scatter(data.Population, data.Profit, label='Training Data')
ax.legend(loc=2)
ax.set_xlabel('Population')
ax.set_ylabel('Profit')
ax.set_title('Predicted Profit vs. Population Size')</code></pre>
<br /><br />
<h5>machine-problem-3-data.txt</h5>
<pre class="line-numbers"><code class="lang-none">6.1101,17.592
5.5277,9.1302
8.5186,13.662
7.0032,11.854
5.8598,6.8233
8.3829,11.886
7.4764,4.3483
8.5781,12
6.4862,6.5987
5.0546,3.8166
5.7107,3.2522
14.164,15.505
5.734,3.1551
8.4084,7.2258
5.6407,0.71618
5.3794,3.5129
6.3654,5.3048
5.1301,0.56077
6.4296,3.6518
7.0708,5.3893
6.1891,3.1386
20.27,21.767
5.4901,4.263
6.3261,5.1875
5.5649,3.0825
18.945,22.638
12.828,13.501
10.957,7.0467
13.176,14.692
22.203,24.147
5.2524,-1.22
6.5894,5.9966
9.2482,12.134
5.8918,1.8495
8.2111,6.5426
7.9334,4.5623
8.0959,4.1164
5.6063,3.3928
12.836,10.117
6.3534,5.4974
5.4069,0.55657
6.8825,3.9115
11.708,5.3854
5.7737,2.4406
7.8247,6.7318
7.0931,1.0463
5.0702,5.1337
5.8014,1.844
11.7,8.0043
5.5416,1.0179
7.5402,6.7504
5.3077,1.8396
7.4239,4.2885
7.6031,4.9981
6.3328,1.4233
6.3589,-1.4211
6.2742,2.4756
5.6397,4.6042
9.3102,3.9624
9.4536,5.4141
8.8254,5.1694
5.1793,-0.74279
21.279,17.929
14.908,12.054
18.959,17.054
7.2182,4.8852
8.2951,5.7442
10.236,7.7754
5.4994,1.0173
20.341,20.992
10.136,6.6799
7.3345,4.0259
6.0062,1.2784
7.2259,3.3411
5.0269,-2.6807
6.5479,0.29678
7.5386,3.8845
5.0365,5.7014
10.274,6.7526
5.1077,2.0576
5.7292,0.47953
5.1884,0.20421
6.3557,0.67861
9.7687,7.5435
6.5159,5.3436
8.5172,4.2415
9.1802,6.7981
6.002,0.92695
5.5204,0.152
5.0594,2.8214
5.7077,1.8451
7.6366,4.2959
5.8707,7.2029
5.3054,1.9869
8.2934,0.14454
13.394,9.0551
5.4369,0.61705</code></pre>

Machine Problem 3

Create a simple Python program for linear regression using randomly generated data sets, which is scattered around a line with a slope of 2 and intercept of -2. Present the regression model coefficient and intercept, coefficient of determination (R2), and root mean squared error (RMSE).

<h5>Code: </h5>
<pre class="line-numbers"><code class="lang-python">import pandas as pd
import numpy as np
import matplotlib.pyplot as plt
from sklearn.linear_model import LinearRegression
from sklearn.metrics import mean_squared_error, r2_score

%matplotlib notebook	

#generating random data with slope=2 and intercept=-2
delta = np.random.uniform(-10,10, size=(20,)) #for generating random data
x = np.arange(20)
y = 2*x-2+delta #y=mx+b; m=slope; b-y-intercept; delta=random scatter
plt.scatter(x,y, c = 'b', label='random data') #scatter plot
#print(x)
#print(y)

#generating the desired line which is y=2x-2
y = 2*x-2 #y=mx+b; m=slope; b-y-intercept
plt.plot(x,y, c='r', linewidth=1, label = 'desired') #plot line

#generating the linear regression from the random data
x = x.reshape(-1, 1)

model = LinearRegression()
model.fit(x, y)

y_predict = model.predict(x)
#print(y_predict)

plt.plot(x, y_predict, 'g', linewidth=3, linestyle=':', dash_capstyle='round', label='output') #plot linear regression

#styling the plot
plt.legend(loc=2)
plt.xticks(np.arange(0, 21, 1))
plt.yticks(np.arange(-10, 50, 10))
plt.show()
plt.savefig('MP4.png')

print("Linear regression coefficient = ", model.coef_[0])
print("Linear regression intercept = ", model.intercept_)
print("coefficient of determination (R\u00b2) = ", r2_score(y, y_predict))
print("root mean squared error (RMSE) = ", np.sqrt(mean_squared_error(y, y_predict)))</code></pre>

Machine Problem 4

Insert your corresponding code in the space provided.

<p>This exam consists of 4 items which is all coding in data visualization using python.</p>
<p><i>Note: Items are jumbled and I don't have the questions.</i></p>
<h5>Item 1</h5>
<pre class="line-numbers"><code class="lang-python">import matplotlib.pyplot as plt

fig, ax = plt.subplots()

x_values = [10, 20, 30]
y_values = [20, 40, 10]
ax.plot(x_values, y_values,':b', label='line1-dotted')

x2_values = [10, 20, 30]
y2_values = [40,10,30]
ax.plot(x2_values, y2_values, '--r', label='line2-dashed')

leg = ax.legend()
plt.xlabel("x-axis")
plt.ylabel("y-axis")

plt.show()</code></pre>
<br /><br />
<h5>Item 2</h5>
<pre class="line-numbers"><code class="lang-python">import matplotlib.pyplot as plt
import numpy as np

x = np.random.randint(100, size=50)
y = np.random.randint(100, size=50)

plt.scatter(x,y, color='g')

plt.xlabel("x-axis")
plt.ylabel("y-axis")

plt.show()</code></pre>
<br /><br />
<h5>Item 3</h5>
<pre class="line-numbers"><code class="lang-python">import matplotlib.pyplot as plt
import numpy as np

ax = plt.axes()

x = np.arange(6)
y = 5 * x

plt.title("y = 5x line graph")
plt.xlabel("x-axis")
plt.ylabel("y-axis")
ax.plot(x, y, c="g")
plt.show()</code></pre>
<br /><br />
<h5>Item 4</h5>
<pre class="line-numbers"><code class="lang-python">import matplotlib.pyplot as plt

x = ['Civil', 'Chemical', 'Mechanical', 'Electronics', 'Electrical', 'Industrial']

enrollees = [22.2, 17.6, 8.8, 8, 7.7, 6.7]

xaxis = np.arange(len(x))

plt.bar(x_pos, enrollees, color='r')
plt.ylabel("Enrollees (in 1000)")

plt.xticks(x_pos, x, rotation=45)
plt.show()</code></pre>
<br /><br />

Examination 2

<h5>Course Outcome 2</h5>
<li>Integrals of Trigonometric Functions</li>
<pre class="line-numbers"><code class="lang-matlab">syms x
int(5*(sec(pi*x))^2)</code></pre>
<br />
<li>Integration by Trigonometric Substitution</li>
<pre class="line-numbers"><code class="lang-matlab">syms x
int(x^2/sqrt(4+x^2))</code></pre>
<br />
<li>Integration by Parts</li>
<pre class="line-numbers"><code class="lang-matlab">syms x
int((exp(2*x))*(x^3+x^2+2*x-1))</code></pre>
<br /><br /><br />


<h5>Course Outcome 3</h5>
<li>Definite Integral</li>
<pre class="line-numbers"><code class="lang-matlab">syms x
int(((x^7+1)*(3*x^2+1)),-2,2)</code></pre>
<br />
<li>Improper Integral</li>
<pre class="line-numbers"><code class="lang-matlab">syms x
int(1/sqrt(4-x^2),0,2)

f(x)=(1/sqrt(4-x.^2));
fplot(1/sqrt(4-x^2),[0,2])
daspect([1 5 1]);
line([2.1,2.1], [0.0]);
grid on</code></pre>
<br />
<li>Area under a cuve</li>
<pre class="line-numbers"><code class="lang-matlab">syms x
int((x^2),1,2)

y = @(x) (x.^2);
x = linspace(0, 1);

inty = cumtrapz(x,y(x));
figure(1)
plot(x, inty, '-k', 'LineWidth', 2)
hold on
patch([x fliplr(x)], [zeros(size(x)) fliplr(inty)], 'b')
grid</code></pre>
<br /><br /><br />

<h5>Course Outcome 4</h5>
<li>Doube integration over nonrectangular regions</li>
<pre class="line-numbers"><code class="lang-matlab">syms x y
int(int(exp(-y^2),y,4*x,4),x,0,1)

clear all, close all; clc
x = 0 : 1;
curve1 = 4+0*x;
curve2 = 4*x;
hold on;
x2 = [x, fliplr(x)];
inBetween = [curve1, fliplr(curve2)];
fill(x2, inBetween, 'b');
plot(x, curve2, 'r', 'LineWidth', 2);
plot(x, curve1, 'r', 'LineWidth', 2);
grid</code></pre>
<br />
<li>Double Integration</li>
<pre class="line-numbers"><code class="lang-matlab">syms x y
int(int(exp(x+y),x,0,x),y,0,1)</code></pre>
<br />
<li>Triple integration</li>
<pre class="line-numbers"><code class="lang-matlab">syms x y z
int(int(int(z*(sin(x)+cos(y)),z,0,1),y,0,pi/2),x,0,pi)</code></pre>

MATH147

Project

<h5>Click on the title of the Laboratory Experiment to download the file.</h5><br />
<p>Laboratory Experiment 1: <a href="https://drive.google.com/file/d/14Ntvc7XQ2diJHB6Gjb467iBtqBonI4AA/view?usp=sharing" target="_blank">Vinegar Analysis</a></p>
<p>Laboratory Experiment 2: <a href="https://drive.google.com/file/d/1sAj30MlYSCYuzUtLoeleyOMX3IgHLzn1/view?usp=sharing" target="_blank">Molar Mass of a Volatile Liquid</a></p>
<p>Laboratory Experiment 3: <a href="https://drive.google.com/file/d/1BFLg_LAzQKweVU1_e6Xp6BKWGilcouie/view?usp=sharing" target="_blank">Calorimetry</a></p>
<p>Laboratory Experiment 4: <a href="https://drive.google.com/file/d/1FIEzmngOi87S0_sUniZHG9Fp5VsRj-Uk/view?usp=sharing" target="_blank">Galvanic Cell, the Nernst Equation</a></p>
<p>Laboratory Experiment 5: <a href="https://drive.google.com/file/d/1K9IM1R-1eXQrCHHNAz47Nv8XDeXHlJdv/view?usp=sharing" target="_blank">Water Analysis</a></p>
<p>Laboratory Experiment 6: <a href="https://drive.google.com/file/d/1PJA6KcVIRGu3j9NGV4Bdznp5RVGcNYZf/view?usp=sharing" target="_blank">Dissolved Oxygen Levels in Natural Waters</a></p>

CM011L

Laboratory Reports

2. Ask for the Base and Exponent and output the computed power

<pre class='lang-cpp line-numbers'><code>#include &lt;iostream&gt;
using namespace std;
int main()
{
 int, base, exp;
 float pow=1;
 cout&lt;&lt;&quot;base: &quot;;
 cin&gt;&gt;base;
 cout&lt;&lt;&quot;exponent: &quot;;
 cin&gt;&gt;exp;
 
 if (exp==0)
 {
  pow=1;
 }
 else if (exp&lt;0)
 {
  int tempexp=exp*-1;
  while (tempexp&gt;0)
  {
   pow*=base;
   tempexp=tempexp-1;
  }
  pow=1/pow;
 }
 else
 {
  int tempexp=exp;
  while (tempexp&gt;0)
  {
   pow*=base;
   tempexp=tempexp-1;
  }
 }
 
 cout&lt;&lt;pow;
}
</code></pre>

3. Ask the user for the value of N and output the nth term of the fibonacci series

<pre class='lang-cpp line-numbers'><code>#include &lt;iostream&gt;
using namespace std;
int main()
{
 int a=0, b=1, ctr=1, n;
 int fib;
 
 cin&gt;&gt;n;
 
 if (n&lt;0)
 {
  cout&lt;&lt;&quot;out of range&quot;;
 }
 else if(n==1)
 {
  cout&lt;&lt;a;
 }
 else if(n==2)
 {
  cout&lt;&lt;b;
 }
 else
 {
  while(ctr&lt;=n)
  {
   fib=a+b;
   a=b;
   b=fib;
   ctr++;
   cout&lt;&lt;fib&lt;&lt;&quot; &quot;;
  }
 }
}</code></pre>

4. Determine if the input number is Prime and Composite.

<pre class='lang-cpp line-numbers'><code>start

factor=2,prime=1
input num

if (num==1 or num==2 or num==3 or num==0)
	print “Prime”
else
	while(factor<=num/2)
		if (num%factor==0)
			prime=0
factor=num
endif
factor++
	endwhile
	
	if (prime==1)
		print “prime”
	else
		print “composite”
	endif
endif

end</code></pre>

5. Ask for a range of number (lower limit and upper limit), and output all Prime numbers from the input range.

<pre class='lang-cpp line-numbers'><code>start

input LL, UL

if(LL>UL)
temp=LL
LL=UL
UL=temp
endif

num=LL
while (num<=UL)
	factor=2
prime=1
	while(factor<=num/2)
		if (num%factor==0)
			prime=0
			factor=num
		endif
		factor++
	endwhile

	if (prime==1)
		print num
	endif
	num++
endwhile

end</code></pre>

6. Determine the product of two input numbers without using multiplication

<pre class='lang-cpp line-numbers'><code>start

ctr=1
product=0

input num1
input num2

if(num<0 and num2<0)
	num1=num1*-1
	num2=num2*-1
elseif(num1>num2)
	temp=num1
	num1=num2
	num2=temp
endif

while(ctr<=num2)
	product=product+num1
	ctr++
endwhile

print product

end</code></pre>

7. Determine modulo division given the dividend and divisor as inputs without using modulo (%) operation

<pre class='lang-cpp line-numbers'><code>start

input dividend
input divisor

tempdivisor=divisor
tempdividend=dividend

while(tempdivisor<=tempdividend)
	tempdividend=tempdividend-tempdivisor
endwhile

print tempdividend

end
</code></pre>

8. Ask for a number (5 digit) and output the reverse order of the number. ex. 23765   === > 56732

<pre class='lang-cpp line-numbers'><code>start

input num

if(num>=10000 and num<=99999)
	while(num!=0)
		temp=num%10
		print temp
		num=num/10
	endwhile
else
	print “out of range”
endif

end</code></pre>

1. Determine the computed Power given Base and Ex (exponent) as user input without using Multiplication. You may use successive Addition.

<pre class='lang-cpp line-numbers'><code>start
int fact = 1

print "Enter a positive integer: "
input num

if (num==0)
	print "invalid"

elseif (num&lt;0)
	print "NA"

elseif (num&gt;0)
	while (i&lt;=num)
		fact=fact * i
		i++
	endwhile
	print factorial
endif

end</code></pre>

Activity 2

2. Determine the factorial of an input number without using multiplication. Use successive addition

<pre class='lang-cpp line-numbers'><code>start
int factorial
int i=1, ifact=1

print "Enter a number: "
input factorial

int tempfact=factorial
int factstore=factorial-1

if (factorial==0)
	print "invalid"
elseif (factorial&lt;0)
	print "Out of range"
else
	while (i&lt;=factorial)
		int tempnew=tempfact
		ifact=1
		while	(ifact&lt;factstore)
			tempfact=tempfact+tempnew
			ifact++
		endwhile
		factstore--
		i++
	endwhile
	print tempfact

end</code></pre>

3. Output or Prints the following pattern. Ask the user for the value of Seed ( number of rows). You can print in the next line by printing '\n' or putting the '\n' inside the double quotes. You may also print a special variable endl.

<ol type="a">
<h5><li><pre>Seed = 4

*****
*****
*****
*****</pre></li></h5>
<pre class='lang-cpp line-numbers'><code>start

int rows
int i=1

print “Enter number of rows: ”
input rows

while (i&lt;=rows)
	print ”*****\n”
	i++
endwhile

end</code></pre>
<br /><br />


<h5><li><pre>Seed = 3

ABCDE
FGHIJ
KLMNO
<i>Note: If the logic run out of letter you just go back to character 'A'</i></pre></li></h5>
<pre class='lang-cpp line-numbers'><code>start

int rows
int i=1, init=1
char out=’A’

print “Enter number of rows: ”
input rows

while (i&lt;=rows)
	while (init&lt;=5)
		print out
		init++
		out++
		if (out&gt;Z)
			out=’A’
		endif
	endwhile
	print endl
	init=1
	i++
endwhile

end</code></pre>
<br /><br />


<h5><li><pre>Seed = 5

    *
   **
  ***
 ****
*****</pre></li></h5>
<pre class='lang-cpp line-numbers'><code>start

int rows
int i=1, i2=1, i3

print “Enter number of rows: ”
input rows

int temprows=rows
i3=temprows
while (i&lt;=rows)
	while (i2&lt;temprows)
		print “ “
		i2++
	endwhile
	i2=1
	while (i3&lt;=rows &amp;&amp; i3&gt;0)
		print “*”
		i3++
	endwhile
	i3=temprows-1
	temprows--
	print endl
	i++
endwhile

end</code></pre>
<br /><br />


<h5><li><pre>Seed = 6

     *
    * *
   * * *
  * * * *
 * * * * *
* * * * * *</pre></li></h5>
<pre class='lang-cpp line-numbers'><code>start

int rows
int i=1, i2=1

print “Enter number of rows: ”
input rows

int temprows=rows
int i3=temprows
while (i&lt;=rows)
	while (i2&lt;temprows)
		print “ “
		i2++
	endwhile
	i2=1
	while (i3&lt;=rows &amp;&amp; i3&gt;0)
		print “* ”
		i3++
	endwhile
	i3=temprows-1
	temprows--
	print endl
	i++
endwhile

end</code></pre>
<br /><br />


<h5><li><pre>Seed = 5

BCDFG
HJKLM
NPQRS
TVWXY
ZBCDF
<i>Note: If the logic run out of letter you just go back to character 'A'</i></pre></li></h5>
<pre class='lang-cpp line-numbers'><code>start

int rows
int i=1, init=1
char out=’A’

print “Enter number of rows: ”
input rows

while (i<=rows)
	while (init<=5)
		if (out==’A’ || out==’E’ || out==’I’ || out==’O’ || out==’U’)
			out++
		endif
		print out
		init++
		out++
		if (out>Z)
			out=’A’
		endif
	endwhile
	print endl
	init=1
	i++
endwhile

end</code></pre>
</ol>

1. Ask a user for 20 numbers, must store in an array. Determine the largest and smallest number.

<h5>Code: </h5>
<pre class='lang-cpp line-numbers'><code>start
	int size=20
	int rane[size]
	int largest, smallest
	print “Enter 20 numbers:”
	for (int a=0; a&lt;size; a++)
		input rane[a]
	end for
	largest=rane[0]
	smallest=rane[0]
	for (int a=0; a&lt;size; a++)
		if (largest&lt;rane[a])
			largest=rane[a]
		end if
		if (smallest&gt;rane[a])
			smallest=rane[a]
		end if
	end for
	print “the largest number is “, largest, endl
	print “the smallest number is “, smallest,
end</code></pre>
<br /><br />

Assignment 3

2. Ask a user for 20 numbers, must store in an array. Determine the mean.

<h5>Code: </h5>
<pre class='lang-cpp line-numbers'><code>start
	int sum=0, mean=0

	for (int a=0; a&lt;size; a++)
		sum = sum+rane[a]
	end for
	
	mean=sum/size	

	print “the mean is “, mean
end</code></pre>
<br /><br />

3. Ask the user for 10 numbers, then reverse the order of the number in the array.

<h5>Code: </h5>
<pre class='lang-cpp line-numbers'><code>start

	int size=10, b=size-1
	int gtech[size]
	int temp
	
	print “Enter 10 numbers:”

	for (int a=0; a&lt;size; a++)
		input gtech[a]
	end for
	
	for (int a=0; a&lt;b; a++)
		gtech[a]=gtech[a]+gtech[b]
		gtech[b]=gtech[a]-gtech[b]
		gtech[a]=gtech[a]-gtech[b]
		b--;
end for

	print “the reverse of the numbers is: ”
	for (int a=0; a&lt;size; a++)
		print gtech[a], “   “
end for

end</code></pre>
<br /><br />

4. Ask the user for 10 numbers and output the number in ascending and descending order.

<h5>Code: </h5>
<pre class='lang-cpp line-numbers'><code>start

	int size=10, temp, temp2
	int gtech[size], tempgtech[size]

	print “Enter 10 numbers:”
	for (int a=0; a&lt;size; a++)
		input gtech[a]
		tempgtech[a]=gtech[a]
	end for
	for (int a=0; a&lt;size; a++)
		for (int b=a; b&lt;size; b++)
			if (gtech[a]&gt;gtech[b])
				temp=gtech[a]
				gtech[a]=gtech[b]
				gtech[b]=temp
			end if
			if (tempgtech[a]&lt;tempgtech[b])
				temp2=tempgtech[a]
				tempgtech[a]= tempgtech[b]
				tempgtech[b]=temp2
			end if
		end for
	end for

	print “the numbers in ascending order; “
for (int a=0; a&lt;size; a++)
		print gtech[a], “   “
	end for

print endl, “the numbers in descending order; “
for (int a=0; a&lt;size; a++)
		print tempgtech[a], “   “
	end for

end</code></pre>
<br /><br />

<h5>Simple Student Records System with Database</h5>
<p>Written in Visual BASIC with MS Access database</p>
<h6>Required:</h6>
<ol>
<li>Add</li>
<li>Edit</li>
<li>Delete</li>
<li>Search</li>
<li>Get Quiz Average of a specific student</li>
</ol> 
<br />
<h6>The Program</h6>
<img class="img-fluid" src="https://i.imgur.com/N8akJYs.png" alt="Final Exam CPE102L" />
<br /><br />
<h6>The Database</h6>
<img class="img-fluid" src="https://i.imgur.com/mJvNmej.png" alt="Databse Schema CPE102L" />
<br /><br /><br />
<h5>Main Form code</h5>
<pre class='lang-basic line-numbers'><code>Public Class frmMain
    Sub read()
        If conn.State = ConnectionState.Open Then conn.Close()
        Dim dt As New DataTable
        adapter.Fill(dt)


        txtStudno.Text = dt.Rows(0).Item(&quot;Student Number&quot;)
        txtfname.Text = dt.Rows(0).Item(&quot;First Name&quot;)
        txtsurname.Text = dt.Rows(0).Item(&quot;Surname&quot;)
        txtgender.Text = dt.Rows(0).Item(&quot;Gender&quot;)
        txtq1.Text = dt.Rows(0).Item(&quot;Quiz 1&quot;)
        txtq2.Text = dt.Rows(0).Item(&quot;Quiz 2&quot;)
        txtq3.Text = dt.Rows(0).Item(&quot;Quiz 3&quot;)
        txtq4.Text = dt.Rows(0).Item(&quot;Quiz 4&quot;)
        dgv.ClearSelection()
    End Sub

    Sub dis()
        cmdUpdate.Enabled = True
        cmdCancel.Enabled = True
        cmdAdd.Enabled = False
        cmdDelete.Enabled = False
        cmdEdit.Enabled = False
        txtsearch.Enabled = False
        cmdsearch.Enabled = False
        txtStudno.Enabled = False
        filter.Enabled = False
        dgv.ClearSelection()

    End Sub

    Sub ena()
        cmdUpdate.Enabled = False
        cmdCancel.Enabled = False
        cmdAdd.Enabled = True
        cmdEdit.Enabled = True
        txtsearch.Enabled = True
        cmdsearch.Enabled = True
        txtStudno.Enabled = True
        filter.Enabled = True

        cmdAdd.Enabled = True
        dgv.ClearSelection()

    End Sub
    Sub clear()
        txtStudno.Text = &quot;&quot;
        txtfname.Text = &quot;&quot;
        txtsurname.Text = &quot;&quot;
        txtgender.Text = &quot;&quot;
        txtq1.Text = &quot;&quot;
        txtq2.Text = &quot;&quot;
        txtq3.Text = &quot;&quot;
        txtq4.Text = &quot;&quot;
        txtgender.SelectedIndex = -1
        dgv.ClearSelection()

    End Sub
    Sub populate()

        sSQL = &quot;select StudNo as [Student Number],fname as [First Name], surname as [Surname], gender as [Gender], q1 as [Quiz 1], q2 as [Quiz 2], q3 as [Quiz 3], q4 as [Quiz 4] from tblstudents order by StudNo&quot;
        execSQL(sSQL, False)
        filldg(sSQL, dgv)
        adapter.Fill(dt)

        dgv.ClearSelection()

    End Sub
    Private Sub DataGridView1_CellContentClick(sender As Object, e As DataGridViewCellEventArgs)

    End Sub

    Private Sub ToolStripLabel1_Click(sender As Object, e As EventArgs)

    End Sub

    Private Sub frmMain_Load(sender As Object, e As EventArgs) Handles MyBase.Load
        ena()
        populate()
        dgv.ClearSelection()
    End Sub

    Private Sub cmdAdd_Click(sender As Object, e As EventArgs) Handles cmdAdd.Click

        Add()

    End Sub

    Private Sub cmdEdit_Click(sender As Object, e As EventArgs) Handles cmdEdit.Click
        If dgv.Rows.Count &gt; 0 Then
            If dgv.SelectedRows.Count &gt; 0 Then
                dis()
                sSQL = &quot;SELECT StudNo as [Student Number],fname as [First Name], surname as [Surname], gender as [Gender], q1 as [Quiz 1], q2 as [Quiz 2], q3 as [Quiz 3], q4 as [Quiz 4] from tblstudents where StudNo=&quot; &amp; dgv.CurrentRow.Cells(&quot;Student Number&quot;).Value &amp; &quot;&quot;
                execSQL(sSQL, False)
                read()
            Else
                    MessageBox.Show(&quot;No record selected!&quot;)

            End If
        Else
            MessageBox.Show(&quot;No records!&quot;)
        End If
    End Sub

    Private Sub cmdCancel_Click(sender As Object, e As EventArgs) Handles cmdCancel.Click
        ena()
        clear()
        populate()
    End Sub

    Private Sub cmdUpdate_Click(sender As Object, e As EventArgs) Handles cmdUpdate.Click
        edit()
    End Sub

    Private Sub cmdDelete_Click(sender As Object, e As EventArgs) Handles cmdDelete.Click
        delete()
    End Sub


    Private Sub txtsearch_TextChanged(sender As Object, e As EventArgs) Handles txtsearch.TextChanged
        search()
    End Sub


    Private Sub cmdquiz_Click(sender As Object, e As EventArgs) Handles cmdquiz.Click
        ave()
    End Sub

    Private Sub filter_SelectedIndexChanged(sender As Object, e As EventArgs) Handles filter.SelectedIndexChanged
        txtsearch.Text = &quot;&quot;
    End Sub
End Class</code></pre>
<br /><br />

<h5>Database connection module</h5>
<pre class='lang-basic line-numbers'><code>Imports System.Data
Imports System.Configuration
Imports System.Data.OleDb
Imports System

Module ModuleConnection
    Public conn As New OleDbConnection
    Public cmd As New OleDbCommand
    Public RD As OleDbDataReader
    Public sSQL As String
    Public adapter As New OleDbDataAdapter
    Public mydataset As New DataSet
    Public dt As New DataTable


    Public Sub execSQL(ByVal query As String, ByVal stat As Boolean)
        Try
            If conn.State = ConnectionState.Open Then conn.Close()
            conn.ConnectionString = &quot;Provider=Microsoft.Jet.OLEDB.4.0;Data Source=|DataDirectory|\students.mdb;User Id=admin;Password=;&quot;
            &#39;&quot;server=RANEGILLIAN\DWHSEASDB;Database=login;Trusted_Connection=True;&quot;
            conn.Open()
            cmd.Connection = conn
            cmd.CommandText() = query




            If stat = False Then
                RD = cmd.ExecuteReader()
            Else
                cmd.ExecuteNonQuery()
            End If
        Catch ex As Exception
            MessageBox.Show(ex.Message)
        End Try
    End Sub

    Public Sub filldg(ByVal query As String, ByRef dg As DataGridView)
        Try
            If conn.State = ConnectionState.Open Then conn.Close()
            cmd = New OleDbCommand(query, conn)
            adapter = New OleDbDataAdapter(cmd)

            mydataset = New DataSet()
            adapter.Fill(mydataset)
            dg.DataSource = &quot;&quot;
            dg.DataSource = mydataset.Tables(0)
            dg.AutoResizeColumns()

        Catch ex As Exception
            MessageBox.Show(ex.Message)
        End Try
    End Sub
End Module</code></pre>
<br /><br />


<h5>[1] Add module code</h5>
<pre class='lang-basic line-numbers'><code>Module ModuleAdd

    Public Sub Add()

        If Len(Trim(frmMain.txtStudno.Text)) = 0 Then
            MessageBox.Show(&quot;Please don&#39;t leave any blanks&quot;)
        ElseIf frmMain.txtStudno.Text &gt; 9999999999 Or frmMain.txtStudno.Text &lt; 1000000000 Then
            MessageBox.Show(&quot;Enter 10 digits student number&quot;)
        ElseIf frmMain.txtfname.Text = &quot;&quot; Or frmMain.txtsurname.Text = &quot;&quot; Or frmMain.txtgender.Text = &quot;&quot; Then
            MessageBox.Show(&quot;Please don&#39;t leave any blanks&quot;)
        ElseIf frmMain.txtq1.Text &gt; 100 Or frmMain.txtq1.Text &lt; 0 Or frmMain.txtq2.Text &gt; 100 Or frmMain.txtq2.Text &lt; 0 Or frmMain.txtq3.Text &gt; 100 Or frmMain.txtq3.Text &lt; 0 Or frmMain.txtq4.Text &gt; 100 Or frmMain.txtq4.Text &lt; 0 Then
            MessageBox.Show(&quot;0-100 range on quizzes&quot;)
        Else
            sSQL = &quot;select StudNo as [Student Number],fname as [First Name], surname as [Surname], gender as [Gender], q1 as [Quiz 1], q2 as [Quiz 2], q3 as [Quiz 3], q4 as [Quiz 4] from tblstudents where Studno=&quot; &amp; frmMain.txtStudno.Text &amp; &quot;&quot;
            execSQL(sSQL, False)

            If RD.Read Then
                MsgBox(&quot;Student with student number of &quot; + frmMain.txtStudno.Text + &quot; already exists!&quot;, MsgBoxStyle.Critical, &quot;Duplicated&quot;)
            Else



                sSQL = &quot;INSERT INTO tblStudents(`StudNo`, `fname`, `surname`, `gender`, `q1`, `q2`, `q3`, `q4`) values (&#39;&quot; &amp; frmMain.txtStudno.Text &amp; &quot;&#39;, &#39;&quot; &amp; frmMain.txtfname.Text &amp; &quot;&#39;, &#39;&quot; &amp; frmMain.txtsurname.Text &amp; &quot;&#39;, &#39;&quot; &amp; frmMain.txtgender.Text &amp; &quot;&#39;, &#39;&quot; &amp; frmMain.txtq1.Text &amp; &quot;&#39;, &#39;&quot; &amp; frmMain.txtq2.Text &amp; &quot;&#39;, &#39;&quot; &amp; frmMain.txtq3.Text &amp; &quot;&#39;, &#39;&quot; &amp; frmMain.txtq4.Text &amp; &quot;&#39;) &quot;
                execSQL(sSQL, True)

                MessageBox.Show(&quot;Record Added&quot;)

                frmMain.clear()
                frmMain.populate()



            End If
        End If
    End Sub

End Module</code></pre>
<br /><br />


<h5>[2] Edit module code</h5>
<pre class='lang-basic line-numbers'><code>Module ModuleUpdate

    Public Sub edit()
        If frmMain.txtfname.Text = &quot;&quot; Or frmMain.txtsurname.Text = &quot;&quot; Or frmMain.txtgender.Text = &quot;&quot; Then
            MessageBox.Show(&quot;Please don&#39;t leave any blanks&quot;)
        ElseIf frmMain.txtq1.Text &gt; 100 Or frmMain.txtq1.Text &lt; 0 Or frmMain.txtq2.Text &gt; 100 Or frmMain.txtq2.Text &lt; 0 Or frmMain.txtq3.Text &gt; 100 Or frmMain.txtq3.Text &lt; 0 Or frmMain.txtq4.Text &gt; 100 Or frmMain.txtq4.Text &lt; 0 Then
            MessageBox.Show(&quot;0-100 range on quizzes&quot;)
        Else
            sSQL = &quot;UPDATE tblStudents SET fname=&#39;&quot; &amp; frmMain.txtfname.Text &amp; &quot;&#39;, surname=&#39;&quot; &amp; frmMain.txtsurname.Text &amp; &quot;&#39;, gender=&#39;&quot; &amp; frmMain.txtgender.Text &amp; &quot;&#39;, q1=&#39;&quot; &amp; frmMain.txtq1.Text &amp; &quot;&#39;, q2=&#39;&quot; &amp; frmMain.txtq2.Text &amp; &quot;&#39;, q3=&#39;&quot; &amp; frmMain.txtq3.Text &amp; &quot;&#39;, q4=&#39;&quot; &amp; frmMain.txtq4.Text &amp; &quot;&#39; where Studno=&quot; &amp; frmMain.txtStudno.Text &amp; &quot;&quot;
            execSQL(sSQL, True)

            MessageBox.Show(&quot;Record Updated&quot;)

            frmMain.clear()
            frmMain.ena()
            frmMain.populate()

        End If
    End Sub

End Module</code></pre>
<br /><br />


<h5>[3] Delete module code</h5>
<pre class='lang-basic line-numbers'><code>Module ModuleDelete

    Public Sub delete()
        If frmMain.dgv.Rows.Count &gt; 0 Then
            If frmMain.dgv.SelectedRows.Count &gt; 0 Then
                If MsgBox(&quot;Are you Sure?&quot;, MsgBoxStyle.YesNo + MsgBoxStyle.Question, &quot;Confirmation&quot;) = MsgBoxResult.Yes Then
                    sSQL = &quot;DELETE from tblStudents where Studno=&quot; &amp; frmMain.dgv.SelectedRows(0).Cells(&quot;Student Number&quot;).Value &amp; &quot;&quot;
                    MessageBox.Show(&quot;Record Deleted!&quot;)
                    execSQL(sSQL, True)

                    frmMain.clear()
                    frmMain.populate()
                End If
            Else
                MessageBox.Show(&quot;No record selected!&quot;)

            End If
        Else
            MessageBox.Show(&quot;No records!&quot;)
        End If

    End Sub


End Module</code></pre>
<br /><br />


<h5>[4] Search module code</h5>
<pre class='lang-basic line-numbers'><code>Module ModuleSearch

    Public Sub search()
        If frmMain.filter.Text = &quot;Student Number&quot; Then
            sSQL = &quot;select StudNo as [Student Number],fname as [First Name], surname as [Surname], gender as [Gender], q1 as [Quiz 1], q2 as [Quiz 2], q3 as [Quiz 3], q4 as [Quiz 4] from tblstudents where StudNo like &#39;&quot; &amp; frmMain.txtsearch.Text &amp; &quot;%&#39;&quot;
            execSQL(sSQL, False)
            filldg(sSQL, frmMain.dgv)
            adapter.Fill(dt)


        ElseIf frmMain.filter.Text = &quot;First Name&quot; Then
            sSQL = &quot;select StudNo as [Student Number],fname as [First Name], surname as [Surname], gender as [Gender], q1 as [Quiz 1], q2 as [Quiz 2], q3 as [Quiz 3], q4 as [Quiz 4] from tblstudents where fname like &#39;&quot; &amp; frmMain.txtsearch.Text &amp; &quot;%&#39;&quot;
            execSQL(sSQL, False)
            filldg(sSQL, frmMain.dgv)
            adapter.Fill(dt)

        ElseIf frmMain.filter.Text = &quot;Surname&quot; Then
            sSQL = &quot;select StudNo as [Student Number],fname as [First Name], surname as [Surname], gender as [Gender], q1 as [Quiz 1], q2 as [Quiz 2], q3 as [Quiz 3], q4 as [Quiz 4] from tblstudents where surname like &#39;&quot; &amp; frmMain.txtsearch.Text &amp; &quot;%&#39;&quot;
            execSQL(sSQL, False)
            filldg(sSQL, frmMain.dgv)
            adapter.Fill(dt)
        Else
            sSQL = &quot;select StudNo as [Student Number],fname as [First Name], surname as [Surname], gender as [Gender], q1 as [Quiz 1], q2 as [Quiz 2], q3 as [Quiz 3], q4 as [Quiz 4] from tblstudents where surname like &#39;&quot; &amp; frmMain.txtsearch.Text &amp; &quot;%&#39; or fname like &#39;&quot; &amp; frmMain.txtsearch.Text &amp; &quot;%&#39; or StudNo like &#39;&quot; &amp; frmMain.txtsearch.Text &amp; &quot;%&#39;&quot;
            execSQL(sSQL, False)
            filldg(sSQL, frmMain.dgv)
            adapter.Fill(dt)
        End If


    End Sub

End Module</code></pre>
<br /><br />


<h5>[5] Get Quiz Average of a specific student code</h5>
<pre class='lang-basic line-numbers'><code>Module ModuleAve
    Public average As Single
    Public sum As Single

    Public Sub ave()

        If frmMain.dgv.Rows.Count &gt; 0 Then
            If frmMain.dgv.SelectedRows.Count &gt; 0 Then
                sum = frmMain.dgv.CurrentRow.Cells(&quot;Quiz 1&quot;).Value + frmMain.dgv.CurrentRow.Cells(&quot;Quiz 2&quot;).Value + frmMain.dgv.CurrentRow.Cells(&quot;Quiz 3&quot;).Value + frmMain.dgv.CurrentRow.Cells(&quot;Quiz 4&quot;).Value
                average = sum / 4

                MsgBox(&quot;The average of Student Number &quot; + frmMain.dgv.CurrentRow.Cells(&quot;Student Number&quot;).Value.ToString + &quot; is &quot; + average.ToString + &quot;%&quot;, MsgBoxStyle.OkOnly + MsgBoxStyle.Information, &quot;Quiz Average&quot;)

                frmMain.clear()
                frmMain.populate()
                frmMain.dgv.ClearSelection()
            Else
                MessageBox.Show(&quot;No record selected!&quot;)

            End If
        Else
            MessageBox.Show(&quot;No records!&quot;)
        End If
    End Sub

End Module</code></pre>
<br /><br />

Final Exam

<h5>Drill1_1</h5>
<pre class="line-numbers"><code class="lang-verilog">//Verilog model of circuit of Fig 1.1
module circuit1_1(A, B, C, X);

	input A, B, C;
	output X;
	wire wire1, wire2, wire3;

	not NOT(wire2, A);
	xor EOR2(wire1, B, C);
	and AND2(wire3, wire1, A);
	nor NOR2(X, wire3, wire2);

endmodule




//Test bench for the Verilog model of Fig 1.1
module testbench1_1;

	reg A, B, C;
	wire Z;
	circuit1_1 tb1(A, B, C, Z);
	initial
	begin
		A=1&#39;b0; B=1&#39;b0; C=1&#39;b0;
		$display(&quot;Simulating output for circuit1_1&quot;);
		$monitor($time,,,&quot;A=%b B=%b C=%b Z=%b&quot;,A,B,C,Z);

		#2 A=1&#39;b0; B=1&#39;b0; C=1&#39;b1;
		#1 A=1&#39;b0; B=1&#39;b1; C=1&#39;b0;
		#1 A=1&#39;b0; B=1&#39;b1; C=1&#39;b1;
		#1 A=1&#39;b1; B=1&#39;b0; C=1&#39;b0;
		#1 A=1&#39;b1; B=1&#39;b0; C=1&#39;b1;
		#1 A=1&#39;b1; B=1&#39;b1; C=1&#39;b0;
		#1 A=1&#39;b1; B=1&#39;b1; C=1&#39;b1;
		#2 $finish;
	end
endmodule</code></pre>
<br /><br />


<h5>Drill1_2</h5>
<pre class="line-numbers"><code class="lang-verilog">//behavioural Verilog code for a simple 1-bit full subtracter.
module full_subtract(diff, borrowOut, a, b, borrowIn);
	output diff;
	output borrowOut;
	input a, b, borrowIn;
	assign {borrowOut, diff}=a-b-borrowIn;
	//result of subtraction is two bits; the MSB is borrowOut and the LSB
	//is diff.
endmodule

module testingFS();

	reg a, b,borrowIn;
	wire diff, borrowOut;
	full_subtract fs(diff, borrowOut, a, b, borrowIn);

	initial begin
	a=1&#39;b1; b=1&#39;b1; borrowIn=1&#39;b0;
	end

	initial begin
	#10 a=1&#39;b1;
	#10 a=1&#39;b0; b=1&#39;b1;
	#10 a=1&#39;b1; b=1&#39;b0;
	#10 borrowIn=1&#39;b1;
	end

	initial begin
	$display(&quot; a b borrowIn difference borrowOut time&quot;);
	$monitor(&quot; %b %b %b %b %b %b &quot;, a, b, borrowIn, diff,
		borrowOut, $time);
	#10 $finish;
	end
endmodule</code></pre>
<br /><br />


<h5>Exercise 1_1</h5>
<pre class="line-numbers"><code class="lang-verilog">module exercise1_1(W, X, Y, Z);

	output [0:3] W;
	input X, Y;
	input Z;
	wire X1, Y1, Z1;

	not G1(X1, X), G2(Y1, Y),G3(Z1, Z);

	nand G4(W[0], X1, Y1, Z1),G5(W[1], X1, Y, Z1),
		G6(W[2], X, Y1, Z1),G7(W[3], X, Y, Z1);
endmodule


module testbenchEx1_1;
	reg X, Y, Z;
	wire [0:3] O;
	exercise1_1 tb1_2(O, X, Y, Z);
	initial
	begin
		X=1&#39;b0; Y=1&#39;b0; Z=1&#39;b0;
		$display(&quot;Simulating output for exercise1_1&quot;);
		$monitor($time,,,&quot;X=%b Y=%b Z=%b O=%b&quot;, X, Y, Z, O);

		#0 X=1&#39;b0; Y=1&#39;b0; Z=1&#39;b0;
		#1 X=1&#39;b0; Y=1&#39;b0; Z=1&#39;b1;
		#1 X=1&#39;b0; Y=1&#39;b1; Z=1&#39;b0;
		#1 X=1&#39;b0; Y=1&#39;b1; Z=1&#39;b1;
		#1 X=1&#39;b1; Y=1&#39;b0; Z=1&#39;b0;
		#1 X=1&#39;b1; Y=1&#39;b0; Z=1&#39;b1;
		#1 X=1&#39;b1; Y=1&#39;b1; Z=1&#39;b0;
		#1 X=1&#39;b1; Y=1&#39;b1; Z=1&#39;b1;
		#2 $finish;
	end
endmodule</code></pre>
<br /><br />


<h5>Exercise1_2</h5>
<pre class="line-numbers"><code class="lang-verilog">//Verilog model of circuit of Fig 1.1
module circuit1_1(A, B, C, X);	

	input 		A, B, C;
	output	X;
	wire		wire1, wire2, wire3;
	
	not		NOT(wire2, A);
	xor		EOR2(wire1, B, C);
	and		AND2(wire3, wire1, A);
	nor		NOR2(X, wire3, wire2);

endmodule

//Test bench for the Verilog model of Fig 1.1
module  testbench1_1;
	
	reg		A, B, C;
	wire		Z;
	circuit1_1	tb1(A, B, C, Z);
	initial
	begin
		$display(&quot;Simulating output for exercise1_2&quot;);

		#1 A=1&#39;b0; B=1&#39;b0; C=1&#39;b0;
		$display($time,,,&quot;A=%b B=%b C=%b Z=0&quot;,A,B,C);
		#1 A=1&#39;b0; B=1&#39;b0; C=1&#39;b1;
		$display($time,,,&quot;A=%b B=%b C=%b Z=%b&quot;,A,B,C,Z);
		#1 A=1&#39;b0; B=1&#39;b1; C=1&#39;b0;
		$display($time,,,&quot;A=%b B=%b C=%b Z=%b&quot;,A,B,C,Z);
		#1 A=1&#39;b0; B=1&#39;b1; C=1&#39;b1;
		$display($time,,,&quot;A=%b B=%b C=%b Z=%b&quot;,A,B,C,Z);
		#1 A=1&#39;b1; B=1&#39;b0; C=1&#39;b0;
		$display($time,,,&quot;A=%b B=%b C=%b Z=%b&quot;,A,B,C,Z);
		#1 A=1&#39;b1; B=1&#39;b0; C=1&#39;b1;
		$display($time,,,&quot;A=%b B=%b C=%b Z=1&quot;,A,B,C);
		#1 A=1&#39;b1; B=1&#39;b1; C=1&#39;b0;
		$display($time,,,&quot;A=%b B=%b C=%b Z=0&quot;,A,B,C);
		#1 A=1&#39;b1; B=1&#39;b1; C=1&#39;b1;
		$display($time,,,&quot;A=%b B=%b C=%b Z=0&quot;,A,B,C);

		#2 $finish;
	end
endmodule</code></pre>
<br /><br />


<h5>Exercise1_3</h5>
<pre class="line-numbers"><code class="lang-verilog">module exercise1_3(
	output	 var1, x_4,
	input 		x_1, x_2, x_3);
	xor		EOR1(x_4, x_1, x_2, x_3);
	xor		EOR2(var1, x_1, x_2, x_3, x_4);
endmodule

//testbench
module testbench1_3;
	reg x_1,x_2,x_3;
	wire var1,x_4;
	exercise1_3 tb1(var1,x_4,x_1,x_2,x_3);
	initial
	begin
		x_1=1&#39;b0; x_2=1&#39;b0; x_3=1&#39;b0;
		$display(&quot;Simulating output for Exercise1_3&quot;);
		$monitor($time,,,&quot;x_1=%b x_2=%b x_3=%b var1=%b x_4=%b&quot;,x_1,x_2,x_3,var1,x_4);

		#1 x_1=1&#39;b0;x_2=1&#39;b0;x_3=1&#39;b1;
		#1 x_1=1&#39;b0;x_2=1&#39;b1;x_3=1&#39;b0;
		#1 x_1=1&#39;b0;x_2=1&#39;b1;x_3=1&#39;b1;
		#1 x_1=1&#39;b1;x_2=1&#39;b0;x_3=1&#39;b0;
		#1 x_1=1&#39;b1;x_2=1&#39;b0;x_3=1&#39;b1;
		#1 x_1=1&#39;b1;x_2=1&#39;b1;x_3=1&#39;b0;
		#1 x_1=1&#39;b1;x_2=1&#39;b1;x_3=1&#39;b1;
		#2 $finish;
	end
endmodule</code></pre>
<br /><br />


<p>Laboratory Report:  <a href="https://drive.google.com/file/d/10qP27yVUw9JKZaJ7A3ADb14Zlftm4bOW/view?usp=sharing" target="_blank">Click here to download the file</a></p>

CPE114L

Experiment 1

<h5>Drill2_1</h5>
<pre class="line-numbers"><code class="lang-verilog">//This Verilog test bench illustrates the different Verilog constants
module drill2_1;
	reg [7:0] a, b, c, d, e, f, g, h;
	reg [9:0] j;
	
	initial begin
		a=5&#39;O37;
		b=3&#39;D4;
		c=7&#39;hx;
		d=8 &#39;h AF;
		e=10&#39;b01;
		f=4&#39;d10;
		g=32;
		h=-5;
		$write(&quot;Testing&quot;);
		j=3.6E2;
		$write(&quot; %o %b %b %h %b&quot;,a,b,c,d,e);
		$write(&quot; %d %d %d  %d&quot;,f,g,h,j);
	end
endmodule</code></pre>
<br /><br />


<h5>Drill2_2</h5>
<pre class="line-numbers"><code class="lang-verilog">//This Verilog test bench illustrates the different Verilog operators
module drill2_2;
	reg [3:0]Ctr, Xnr, Fdr;
	initial begin
		Ctr=4'd0; Fdr=4'd11;
 		#5 Xnr = (Ctr !=0) ? (Ctr *+ 1) : ^Fdr;
		#10 $display(Xnr);
		#15 Xnr=-9%2; Fdr=52<8'hFF;
		#20 $display(Xnr," ",Fdr);
		#25 Ctr=Xnr&&Fdr; Fdr=Xnr&Fdr;
		#30 $display(Ctr,Fdr);
		#35 Ctr=Ctr<<2; Fdr=Xnr>>1;
		#40 $display(Ctr, Fdr);
		#100 $finish;
	end
endmodule</code></pre>
<br /><br />


<h5>Drill2_3</h5>
<pre class="line-numbers"><code class="lang-verilog">`timescale 10 ns / 100 ps
/*The time unit is set to 10 ns. During the simulation all delay values will be multiplied by 10 ns, and all delays will be rounded with 100 ps precision.*/

`define SIZE 8
`define STOP $finish
`define REGME reg [8*31:0]
`ifdef TEST_1
	`include &quot;drill1_1.vl&quot;
`else
	`include &quot;drill1_2.vl&quot;
`endif

module testbench;
	`REGME	regVar;
	reg	a, b,borrowIn;
	wire	diff, borrowOut;
	full_subtract		fs(diff, borrowOut, a, b, borrowIn);
	
	initial begin
		a=1&#39;b1; b=1&#39;b1; borrowIn=1&#39;b0;
	end

	initial begin
		#10 a=1&#39;b1;
		#10 a=1&#39;b0; b=1&#39;b1;
		#10 a=1&#39;b1; b=1&#39;b0;
		#10 borrowIn=1&#39;b1;
	end

	initial begin
		$display(&quot;    a     b    borrowIn    difference   borrowOut  time&quot;);
		$monitor(&quot;%b  %b     %b    %b    %b   %d&quot;, a, b, borrowIn, diff, borrowOut, $time);
	#10 `STOP;
	end
endmodule</code></pre>
<br /><br />


<h5>Exercise2_1</h5>
<pre class="line-numbers"><code class="lang-verilog">//exercise2_1
module exercise2_1;
	reg[0:7] a;
	reg [8:0] b,c,d,e,f,g,h,i,j;
	
	initial begin
		a = 8&#39;h F1;
		b = 2E4;
		c = 8&#39;h 48;
		d = 8&#39;h 65;
		e = 8&#39;h 6c;
		f = 8&#39;h 6c;
		g = 8&#39;h 6f;
		$display(&quot;%h %d&quot;, a, b,);
		$display(&quot;\\&quot;,&quot; %% &quot;, &quot;\t &quot;,&quot;\&quot;&quot;);
		$display(&quot;%c%C%C%C%C&quot;,c,d,e,f,g);
	end
endmodule </code></pre>
<br /><br />


<h5>Exercise2_2</h5>
<pre class="line-numbers"><code class="lang-verilog">//exercise2_2
`timescale 1s / 100 ns
	`include &quot;drill1_2.vl&quot;
module testbench;
	reg a,b,borrowIn;
	wire diff,borrowOut;
	full_subtract fs(diff,borrowOut,a,b,borrowIn);

	initial begin
		a = 1&#39;b1;
		b = 1&#39;b1;
		borrowIn = 1&#39;b0;
		#10 a = 1&#39;b1;
		#10 a = 1&#39;b0; b = 1&#39;b1;
		#10 a = 1&#39;b1; b = 1&#39;b0;
		#10 borrowIn = 1&#39;b1;
	end
initial begin
	$display(&quot; a b borrowIn difference borrowOut time&quot;);
	$monitor(&quot; %b %b %b %b %b %d &quot;, a, b, borrowIn, diff, borrowOut, $time);
	#10 $finish;
end
endmodule</code></pre>
<br /><br />


<h5>Exercise2_3</h5>
<pre class="line-numbers"><code class="lang-verilog">//exercise2_3
`define pi 3.1416
module exercise2_3;
	real r,s,AnsrRem;
	initial begin
		r = 9;
		s = 4/3;
		AnsrRem = s*`pi*r*r*r;
		$display(&quot;The volume of the cylinder is equal to &quot;, AnsrRem, &quot; cubic units&quot;);
	end
endmodule</code></pre>
<br /><br />


<p>Laboratory Report:  <a href="https://drive.google.com/file/d/1eqKqyg2ZVgOi2bSJ2A8Y4ENaK5EfR8RF/view?usp=sharing" target="_blank">Click here to download the file</a></p>

Experiment 2

<h5>Drill3_1</h5>
<pre class="line-numbers"><code class="lang-verilog">//Verilog model of circuit of Fig 2.1
module circuit2_1(V, W, X, Y, Z, out1);

	input V, W, X, Y, Z;
	output out1;
	wire Vnot, Wnot, Xnot, Ynot, Znot, or1, or2, or3;
	
	not U1(Vnot, V), U2(Wnot, W), U3(Xnot, X);
	not Ur(Ynot, Y), U5(Znot, Z);
	and U7(or1, Vnot, Wnot, Znot), U8(or2, W, Ynot, Z);
	and U9(or3, V, X, Z);
	or U6(out1, or1, or2, or3);

endmodule

module test2_1;
	wire w1;
	reg x1, x2, x3, x4, x5;
	
	circuit2_1 test2_1(x1, x2, x3, x4, x5, w1);
	initial begin
		x1=1&#39;b0; x2=1&#39;b0; x3=1&#39;b0; x4=1&#39;b0; x5=1&#39;b0;
		#100 $finish;
	end
	
	initial begin
		#2 $display(x1,x2,x3,x4,x5,&quot; &quot;,w1);
		#2 x1=1&#39;b0; x2=1&#39;b0; x3=1&#39;b0; x4=1&#39;b1; x5=1&#39;b0; //2
		#2 $display(x1,x2,x3,x4,x5,&quot; &quot;,w1);
		#2 x1=1&#39;b0; x2=1&#39;b0; x3=1&#39;b1; x4=1&#39;b0; x5=1&#39;b0; //4
		#2 $display(x1,x2,x3,x4,x5,&quot; &quot;,w1);
		#2 x1=1&#39;b0; x2=1&#39;b0; x3=1&#39;b1; x4=1&#39;b1; x5=1&#39;b0; //6
		#2 $display(x1,x2,x3,x4,x5,&quot; &quot;,w1);
		#2 x1=1&#39;b0; x2=1&#39;b1; x3=1&#39;b0; x4=1&#39;b0; x5=1&#39;b1; //9
		#2 $display(x1,x2,x3,x4,x5,&quot; &quot;,w1);
		#2 x1=1&#39;b0; x2=1&#39;b1; x3=1&#39;b1; x4=1&#39;b0; x5=1&#39;b1; //13
		#2 $display(x1,x2,x3,x4,x5,&quot; &quot;,w1);
		#2 x1=1&#39;b1; x2=1&#39;b0; x3=1&#39;b1; x4=1&#39;b0; x5=1&#39;b1; //21
		#2 $display(x1,x2,x3,x4,x5,&quot; &quot;,w1);
	end
endmodule</code></pre>
<br /><br />


<h5>Drill3_2</h5>
<pre class="line-numbers"><code class="lang-verilog">module test2_2;
	reg [3:0]A;
	reg [1:0]sel;
	wire Out2;
	
	initial begin
		$display(&quot; TIME A select Output&quot;);
		$monitor($time,,,,,,,&quot;%h %d %b&quot;,A, sel, Out2);
		#50 A=4&#39;hE; sel=2&#39;b00;
		#50 A=4&#39;hA; sel=2&#39;b11;
		#50 A=4&#39;hC; sel=2&#39;b10;
		#50 A=4&#39;hB; sel=2&#39;b01;
		#50 A=4&#39;h0; sel=2&#39;b01;
		#50 $finish;
	end
	
	circuit2_2 t2_2(A, sel, Out2);
endmodule

module circuit2_2(input [3:0]I, input [1:0]S, output Out1);
	wire [3:0]In;
	wire S0not, S1not;
	not #(2) (S0not, S[0]);
	not #(2) (S1not, S[1]);
	and #(5) (In[0], I[0], S0not, S1not);
	and #(5) (In[1], I[1], S[0], S1not);
	and #(5) (In[2], I[2], S0not, S[1]);
	and #(5) (In[3], I[3], S[0], S[1]);
	or #(5) (Out1, In[0], In[1], In[2], In[3]);
endmodule</code></pre>
<br /><br />


<h5>Exercise3_1</h5>
<pre class="line-numbers"><code class="lang-verilog">module exercise3_1(x, y, out1, out2, out3);
	input x, y;
	output out1, out2, out3;
	
	buf U1(out1, x);
	nand U2(out2, x, y);
	xnor U3(out3, x, y);
	
	
endmodule

module start3_1;
	wire w1, w2, w3;
	reg x1, y1;
	
	exercise3_1 start3_1(x1, y1, w1, w2, w3);
	initial begin
		x1=1&#39;b0; y1=1&#39;b0;
		#200 $finish;
	end
	initial begin
		#2 $display(&quot;Truth table of buf: &quot;);
		#2 x1=1&#39;b0;
		#2 $display(&quot;x&quot;, &quot; &quot;, &quot;out&quot;);
		#2 $display(x1,&quot;  &quot;,w1);
		#2 x1=1&#39;b1;
		#2 $display(x1,&quot;  &quot;,w1);
		#2 x1=1&#39;bx;
		#2 $display(x1,&quot;  &quot;,w1);
		#2 x1=1&#39;bz;
		#2 $display(x1,&quot;  &quot;,w1);
		#2 $display(&quot;&quot;);
		
		#2 $display(&quot;Truth table for nand: &quot;);
		#2 x1=1&#39;b0; y1=1&#39;b0;
		#2 $display(&quot;x&quot;, &quot; &quot;, &quot;y&quot;, ,&quot; &quot;, &quot;out&quot;);
		#2 $display(x1, &quot; &quot;,y1, &quot;   &quot;, w2);
		#2 x1=1&#39;b0; y1=1&#39;b1;
		#2 $display(x1, &quot; &quot;,y1, &quot;   &quot;, w2);
		#2 x1=1&#39;b0; y1=1&#39;bx;
		#2 $display(x1, &quot; &quot;,y1, &quot;   &quot;, w2);
		#2 x1=1&#39;b0; y1=1&#39;bz;
		#2 $display(x1, &quot; &quot;,y1, &quot;   &quot;, w2);
		
		#2 x1=1&#39;b1; y1=1&#39;b0;
		#2 $display(x1, &quot; &quot;,y1, &quot;   &quot;, w2);
		#2 x1=1&#39;b1; y1=1&#39;b1;
		#2 $display(x1, &quot; &quot;,y1, &quot;   &quot;, w2);
		#2 x1=1&#39;b1; y1=1&#39;bx;
		#2 $display(x1, &quot; &quot;,y1, &quot;   &quot;, w2);
		#2 x1=1&#39;b1; y1=1&#39;bz;
		#2 $display(x1, &quot; &quot;,y1, &quot;   &quot;, w2);
		
		#2 x1=1&#39;bx; y1=1&#39;b0;
		#2 $display(x1, &quot; &quot;,y1, &quot;   &quot;, w2);
		#2 x1=1&#39;bx; y1=1&#39;b1;
		#2 $display(x1, &quot; &quot;,y1, &quot;   &quot;, w2);
		#2 x1=1&#39;bx; y1=1&#39;bx;
		#2 $display(x1, &quot; &quot;,y1, &quot;   &quot;, w2);
		#2 x1=1&#39;bx; y1=1&#39;bz;
		#2 $display(x1, &quot; &quot;,y1, &quot;   &quot;, w2);
		
		#2 x1=1&#39;bz; y1=1&#39;b0;
		#2 $display(x1, &quot; &quot;,y1, &quot;   &quot;, w2);
		#2 x1=1&#39;bz; y1=1&#39;b1;
		#2 $display(x1, &quot; &quot;,y1, &quot;   &quot;, w2);
		#2 x1=1&#39;bz; y1=1&#39;bx;
		#2 $display(x1, &quot; &quot;,y1, &quot;   &quot;, w2);
		#2 x1=1&#39;bz; y1=1&#39;bz;
		#2 $display(x1, &quot; &quot;,y1, &quot;   &quot;, w2);
		#2 $display(&quot;&quot;);
		
		#2 $display(&quot;Truth table for xnor: &quot;);
		#2 x1=1&#39;b0; y1=1&#39;b0;
		#2 $display(&quot;x&quot;, &quot; &quot;, &quot;y&quot;, ,&quot; &quot;, &quot;out&quot;);
		#2 $display(x1, &quot; &quot;,y1, &quot;   &quot;, w3);
		#2 x1=1&#39;b0; y1=1&#39;b1;
		#2 $display(x1, &quot; &quot;,y1, &quot;   &quot;, w3);
		#2 x1=1&#39;b0; y1=1&#39;bx;
		#2 $display(x1, &quot; &quot;,y1, &quot;   &quot;, w3);
		#2 x1=1&#39;b0; y1=1&#39;bz;
		#2 $display(x1, &quot; &quot;,y1, &quot;   &quot;, w3);
		
		#2 x1=1&#39;b1; y1=1&#39;b0;
		#2 $display(x1, &quot; &quot;,y1, &quot;   &quot;, w3);
		#2 x1=1&#39;b1; y1=1&#39;b1;
		#2 $display(x1, &quot; &quot;,y1, &quot;   &quot;, w3);
		#2 x1=1&#39;b1; y1=1&#39;bx;
		#2 $display(x1, &quot; &quot;,y1, &quot;   &quot;, w3);
		#2 x1=1&#39;b1; y1=1&#39;bz;
		#2 $display(x1, &quot; &quot;,y1, &quot;   &quot;, w3);
		
		#2 x1=1&#39;bx; y1=1&#39;b0;
		#2 $display(x1, &quot; &quot;,y1, &quot;   &quot;, w3);
		#2 x1=1&#39;bx; y1=1&#39;b1;
		#2 $display(x1, &quot; &quot;,y1, &quot;   &quot;, w3);
		#2 x1=1&#39;bx; y1=1&#39;bx;
		#2 $display(x1, &quot; &quot;,y1, &quot;   &quot;, w3);
		#2 x1=1&#39;bx; y1=1&#39;bz;
		#2 $display(x1, &quot; &quot;,y1, &quot;   &quot;, w3);
		
		#2 x1=1&#39;bz; y1=1&#39;b0;
		#2 $display(x1, &quot; &quot;,y1, &quot;   &quot;, w3);
		#2 x1=1&#39;bz; y1=1&#39;b1;
		#2 $display(x1, &quot; &quot;,y1, &quot;   &quot;, w3);
		#2 x1=1&#39;bz; y1=1&#39;bx;
		#2 $display(x1, &quot; &quot;,y1, &quot;   &quot;, w3);
		#2 x1=1&#39;bz; y1=1&#39;bz;
		#2 $display(x1, &quot; &quot;,y1, &quot;   &quot;, w3);
		#2 $display(&quot;&quot;);
	end
endmodule</code></pre>
<br /><br />


<h5>Exercise3_2</h5>
<pre class="line-numbers"><code class="lang-verilog">module exercise3_2(w, x, y, z, out1, out2, out3, out4);
	input w, x, y, z;
	output out1, out2, out3, out4;
	wire wNot, xNot, yNot, zNot, and1, and2, and3, and4, and5, and6;
	
	not U1(wNot, w);
	not U2(xNot, x);
	not U3(yNot, y);
	not U4(zNot, z);
	
	//1000
	buf U5(out1, x);
	
	//0100
	and U6(and1, x, z);
	and U7(and2, x, y);
	or U8(out2, and1, and2);
	
	//0010
	and U9(and3, yNot, zNot);
	and U10(and4, y, z);
	or U11(out3, and3, and4);
	
	//0001
	buf U14(out4, zNot);
	
endmodule

module start3_2;
	wire o1, o2, o3, o4;
	reg w1, x1, y1, z1;
	
	exercise3_2 start3_2(w1, x1, y1, z1, o1, o2, o3, o4);
	initial begin
		w1=1&#39;bx; x1=1&#39;bx; y1=1&#39;bx; z1=1&#39;bx;
		#300 $finish;
	end
	
	initial begin
		#2 $display(&quot;BCD to 9&#39;s Complement Truth Table: &quot;);
		#2 $display(&quot;--BCD--&quot;, &quot;  --9&#39;s Comp--&quot;);
		#2 $display(&quot;w&quot;, &quot; &quot;, &quot;x&quot;, &quot; &quot;, &quot;y&quot;, &quot; &quot;, &quot;z&quot;, &quot;   &quot;, &quot;Q1&quot;, &quot; &quot;, &quot;Q2&quot;, &quot; &quot;, &quot;Q3&quot;, &quot; &quot;, &quot;Q4&quot;);
		#2 $display(w1, &quot; &quot;, x1, &quot; &quot;, y1, &quot; &quot;, z1, &quot;   &quot;, o1, &quot;  &quot;, o2, &quot;  &quot;, o3, &quot;  &quot;, o4);
		#2 w1=1&#39;bx; x1=1&#39;bx; y1=1&#39;bx; z1=1&#39;bx;
		#2 $display(w1, &quot; &quot;, x1, &quot; &quot;, y1, &quot; &quot;, z1, &quot;   &quot;, o1, &quot;  &quot;, o2, &quot;  &quot;, o3, &quot;  &quot;, o4);
		#2 w1=1&#39;bx; x1=1&#39;bx; y1=1&#39;bx; z1=1&#39;bx;
		#2 $display(w1, &quot; &quot;, x1, &quot; &quot;, y1, &quot; &quot;, z1, &quot;   &quot;, o1, &quot;  &quot;, o2, &quot;  &quot;, o3, &quot;  &quot;, o4);
		#2 w1=1&#39;bx; x1=1&#39;bx; y1=1&#39;bx; z1=1&#39;bx;
		#2 $display(w1, &quot; &quot;, x1, &quot; &quot;, y1, &quot; &quot;, z1, &quot;   &quot;, o1, &quot;  &quot;, o2, &quot;  &quot;, o3, &quot;  &quot;, o4);
		#2 w1=1&#39;bx; x1=1&#39;bx; y1=1&#39;bx; z1=1&#39;bx;
		#2 $display(w1, &quot; &quot;, x1, &quot; &quot;, y1, &quot; &quot;, z1, &quot;   &quot;, o1, &quot;  &quot;, o2, &quot;  &quot;, o3, &quot;  &quot;, o4);
		#2 w1=1&#39;bx; x1=1&#39;bx; y1=1&#39;bx; z1=1&#39;bx;
		#2 $display(w1, &quot; &quot;, x1, &quot; &quot;, y1, &quot; &quot;, z1, &quot;   &quot;, o1, &quot;  &quot;, o2, &quot;  &quot;, o3, &quot;  &quot;, o4);
		#2 w1=1&#39;bx; x1=1&#39;bx; y1=1&#39;bx; z1=1&#39;bx;
		#2 $display(w1, &quot; &quot;, x1, &quot; &quot;, y1, &quot; &quot;, z1, &quot;   &quot;, o1, &quot;  &quot;, o2, &quot;  &quot;, o3, &quot;  &quot;, o4);
		#2 w1=1&#39;bx; x1=1&#39;bx; y1=1&#39;bx; z1=1&#39;bx;
		#2 $display(w1, &quot; &quot;, x1, &quot; &quot;, y1, &quot; &quot;, z1, &quot;   &quot;, o1, &quot;  &quot;, o2, &quot;  &quot;, o3, &quot;  &quot;, o4);
		#2 w1=1&#39;bx; x1=1&#39;bx; y1=1&#39;bx; z1=1&#39;bx;
		#2 $display(w1, &quot; &quot;, x1, &quot; &quot;, y1, &quot; &quot;, z1, &quot;   &quot;, o1, &quot;  &quot;, o2, &quot;  &quot;, o3, &quot;  &quot;, o4);
		#2 w1=1&#39;b1; x1=1&#39;b0; y1=1&#39;b0; z1=1&#39;b1;
		#2 $display(w1, &quot; &quot;, x1, &quot; &quot;, y1, &quot; &quot;, z1, &quot;   &quot;, o1, &quot;  &quot;, o2, &quot;  &quot;, o3, &quot;  &quot;, o4);
		#2 w1=1&#39;b1; x1=1&#39;b0; y1=1&#39;b1; z1=1&#39;b0;
		#2 $display(w1, &quot; &quot;, x1, &quot; &quot;, y1, &quot; &quot;, z1, &quot;   &quot;, o1, &quot;  &quot;, o2, &quot;  &quot;, o3, &quot;  &quot;, o4);
		#2 w1=1&#39;b1; x1=1&#39;b0; y1=1&#39;b1; z1=1&#39;b1;
		#2 $display(w1, &quot; &quot;, x1, &quot; &quot;, y1, &quot; &quot;, z1, &quot;   &quot;, o1, &quot;  &quot;, o2, &quot;  &quot;, o3, &quot;  &quot;, o4);
		#2 w1=1&#39;b1; x1=1&#39;b1; y1=1&#39;b0; z1=1&#39;b0;
		#2 $display(w1, &quot; &quot;, x1, &quot; &quot;, y1, &quot; &quot;, z1, &quot;   &quot;, o1, &quot;  &quot;, o2, &quot;  &quot;, o3, &quot;  &quot;, o4);
		#2 w1=1&#39;b1; x1=1&#39;b1; y1=1&#39;b0; z1=1&#39;b1;
		#2 $display(w1, &quot; &quot;, x1, &quot; &quot;, y1, &quot; &quot;, z1, &quot;   &quot;, o1, &quot;  &quot;, o2, &quot;  &quot;, o3, &quot;  &quot;, o4);
		#2 w1=1&#39;b1; x1=1&#39;b1; y1=1&#39;b1; z1=1&#39;b0;
		#2 $display(w1, &quot; &quot;, x1, &quot; &quot;, y1, &quot; &quot;, z1, &quot;   &quot;, o1, &quot;  &quot;, o2, &quot;  &quot;, o3, &quot;  &quot;, o4);
		#2 w1=1&#39;b1; x1=1&#39;b1; y1=1&#39;b1; z1=1&#39;b1;
		#2 $display(w1, &quot; &quot;, x1, &quot; &quot;, y1, &quot; &quot;, z1, &quot;   &quot;, o1, &quot;  &quot;, o2, &quot;  &quot;, o3, &quot;  &quot;, o4);
		#2 $display(&quot; &quot;);
	end
endmodule</code></pre>
<br /><br />


<h5>Exercise3_3</h5>
<pre class="line-numbers"><code class="lang-verilog">//VERILOG FOR 2-BIT BY 2-BIT MULTIPLIER USING HALF ADDERS
module exercise3_3(a0,a1,b0,b1,p0,p1,p2,p3);
	input 		a0,a1,b0,b1;
	output 		p0,p1,p2,p3;
	wire 		and2,and3,and4,andd1;
	and		A1(p0,a0,b0), A2(and2,a1,b0), A3(and3,a0,b1), A4(and4,a1,b1);
	xor		X1(p1,and2,and3), X2(p2,andd1,and4);
	and		AA1(andd1,and2,and3), AA2(p3, andd1, and4);
endmodule

module testEx3_3;
	wire 	o1,o2,o3,o4;
	reg	ia1,ia2,ib1,ib2;

	exercise3_3	testEx3_3(ia1,ia2,ib1,ib2,o1,o2,o3,o4);

	initial begin
		#2 $display(&quot;a0 a1 b0 b1     product&quot;);
		ia1=1&#39;b0;ia2=1&#39;b0;ib1=1&#39;b0;ib2=1&#39;b0;	//0
		#100 $finish;
	end

	initial begin
		#2 $display(ia1,&quot;  &quot;,ia2,&quot;  &quot;,ib1,&quot;  &quot;,ib2, &quot;      &quot;,o1,o2,o3,o4);
		#2 ia1=1&#39;b0;ia2=1&#39;b0;ib1=1&#39;b0;ib2=1&#39;b1;
		#2 $display(ia1,&quot;  &quot;,ia2,&quot;  &quot;,ib1,&quot;  &quot;,ib2, &quot;      &quot;,o1,o2,o3,o4);
		#2 ia1=1&#39;b0;ia2=1&#39;b0;ib1=1&#39;b1;ib2=1&#39;b0;
		#2 $display(ia1,&quot;  &quot;,ia2,&quot;  &quot;,ib1,&quot;  &quot;,ib2, &quot;      &quot;,o1,o2,o3,o4);
		#2 ia1=1&#39;b0;ia2=1&#39;b0;ib1=1&#39;b1;ib2=1&#39;b1;
		#2 $display(ia1,&quot;  &quot;,ia2,&quot;  &quot;,ib1,&quot;  &quot;,ib2, &quot;      &quot;,o1,o2,o3,o4);
		#2 ia1=1&#39;b0;ia2=1&#39;b1;ib1=1&#39;b0;ib2=1&#39;b0;
		#2 $display(ia1,&quot;  &quot;,ia2,&quot;  &quot;,ib1,&quot;  &quot;,ib2, &quot;      &quot;,o1,o2,o3,o4);
		#2 ia1=1&#39;b0;ia2=1&#39;b1;ib1=1&#39;b0;ib2=1&#39;b1;
		#2 $display(ia1,&quot;  &quot;,ia2,&quot;  &quot;,ib1,&quot;  &quot;,ib2, &quot;      &quot;,o1,o2,o3,o4);
		#2 ia1=1&#39;b0;ia2=1&#39;b1;ib1=1&#39;b1;ib2=1&#39;b0;
		#2 $display(ia1,&quot;  &quot;,ia2,&quot;  &quot;,ib1,&quot;  &quot;,ib2, &quot;      &quot;,o1,o2,o3,o4);
		#2 ia1=1&#39;b0;ia2=1&#39;b1;ib1=1&#39;b1;ib2=1&#39;b1;
		#2 $display(ia1,&quot;  &quot;,ia2,&quot;  &quot;,ib1,&quot;  &quot;,ib2, &quot;      &quot;,o1,o2,o3,o4);
		#2 ia1=1&#39;b1;ia2=1&#39;b0;ib1=1&#39;b0;ib2=1&#39;b0;
		#2 $display(ia1,&quot;  &quot;,ia2,&quot;  &quot;,ib1,&quot;  &quot;,ib2, &quot;      &quot;,o1,o2,o3,o4);
		#2 ia1=1&#39;b1;ia2=1&#39;b0;ib1=1&#39;b0;ib2=1&#39;b1;
		#2 $display(ia1,&quot;  &quot;,ia2,&quot;  &quot;,ib1,&quot;  &quot;,ib2, &quot;      &quot;,o1,o2,o3,o4);
		#2 ia1=1&#39;b1;ia2=1&#39;b0;ib1=1&#39;b1;ib2=1&#39;b0;
		#2 $display(ia1,&quot;  &quot;,ia2,&quot;  &quot;,ib1,&quot;  &quot;,ib2, &quot;      &quot;,o1,o2,o3,o4);
		#2 ia1=1&#39;b1;ia2=1&#39;b0;ib1=1&#39;b1;ib2=1&#39;b1;
		#2 $display(ia1,&quot;  &quot;,ia2,&quot;  &quot;,ib1,&quot;  &quot;,ib2, &quot;      &quot;,o1,o2,o3,o4);
		#2 ia1=1&#39;b1;ia2=1&#39;b1;ib1=1&#39;b0;ib2=1&#39;b0;
		#2 $display(ia1,&quot;  &quot;,ia2,&quot;  &quot;,ib1,&quot;  &quot;,ib2, &quot;      &quot;,o1,o2,o3,o4);
		#2 ia1=1&#39;b1;ia2=1&#39;b1;ib1=1&#39;b0;ib2=1&#39;b1;
		#2 $display(ia1,&quot;  &quot;,ia2,&quot;  &quot;,ib1,&quot;  &quot;,ib2, &quot;      &quot;,o1,o2,o3,o4);
		#2 ia1=1&#39;b1;ia2=1&#39;b1;ib1=1&#39;b1;ib2=1&#39;b0;
		#2 $display(ia1,&quot;  &quot;,ia2,&quot;  &quot;,ib1,&quot;  &quot;,ib2, &quot;      &quot;,o1,o2,o3,o4);
		#2 ia1=1&#39;b1;ia2=1&#39;b1;ib1=1&#39;b1;ib2=1&#39;b1;
		#2 $display(ia1,&quot;  &quot;,ia2,&quot;  &quot;,ib1,&quot;  &quot;,ib2, &quot;      &quot;,o1,o2,o3,o4);
	end
endmodule</code></pre>
<br /><br />


<p>Laboratory Report:  <a href="https://drive.google.com/file/d/1CaoYm_Kp6cK5vwFEfHQdlnO0nyeq8uv3/view?usp=sharing" target="_blank">Click here to download the file</a></p>

Experiment 3

<h5>Drill4_1</h5>
<pre class="line-numbers"><code class="lang-verilog">primitive Majority3 ( Z, A, B, C ) ;
	input A, B, C ;
	output Z ;
	table
	// A B C Z
	0 0 ? : 0 ;
	0 ? 0 : 0 ;
	? 0 0 : 0 ;
	1 1 ? : 1 ;
	1 ? 1 : 1 ;
	? 1 1 : 1 ;
	endtable
endprimitive

module testprimitive1;
	reg A, B, C;
	wire X;
	Majority3 (X,A,B,C);
	initial begin
		A=1&#39;b0;B=1&#39;b0;C=1&#39;b0;
		$display(&quot; A B C X&quot;);
		$monitor(&quot; %b %b %b %b&quot;,A,B,C,X);
		#2 A=1&#39;b0; B=1&#39;b0; C=1&#39;b0;
		#2 A=1&#39;b0; B=1&#39;b0; C=1&#39;b1;
		#2 A=1&#39;b0; B=1&#39;b1; C=1&#39;b0;
		#2 A=1&#39;b0; B=1&#39;b1; C=1&#39;b1;
		#2 A=1&#39;b1; B=1&#39;b0; C=1&#39;b0;
		#2 A=1&#39;b1; B=1&#39;b0; C=1&#39;b1;
		#2 A=1&#39;b1; B=1&#39;b1; C=1&#39;b0;
		#2 A=1&#39;b1; B=1&#39;b1; C=1&#39;b1;
		#2 $finish;
	end
endmodule</code></pre>


<br /><br />


<h5>Drill4_2</h5>
<pre class="line-numbers"><code class="lang-verilog">primitive T_FF(F, clk, T);
	input clk, T;
	output F;
	reg F;
	
	initial F=0;
	
	table
	// CLK T : F(STATE) : F(NEXT)
	(01) ? : x : 0 ;
	(01) 0 : 0 : 0 ;
	(01) 0 : 1 : 1 ;
	(01) 1 : 0 : 1 ;
	(01) 1 : 1 : 0 ;
	(10) ? : x : 0 ;
	(10) 0 : 0 : 0 ;
	(10) 0 : 1 : 1 ;
	(10) 1 : 0 : 0 ;
	(10) 1 : 1 : 1 ;
	endtable
endprimitive

module pri;

	reg x, clk;
	wire y;
	
	T_FF TF(y, clk, x);
	
	initial begin
		x=0; clk=0;
	end
	
	always #1 clk=!clk;
	
	initial begin
		x=0;
		#4 x=1;
		repeat(8)
		#8 x=~x;
	end
	
	initial begin
		$display(&quot; TIME clk T Q&quot;);
		$monitor($time,,,&quot; %b %b %b &quot;,clk, x, y);
		#16 $finish;
	end
endmodule</code></pre>


<br /><br />


<h5>Exercise4_1</h5>
<pre class="line-numbers"><code class="lang-verilog">primitive DemuxD0(D, Y, S0, S1, S2);
	input Y, S0, S1, S2;
	output D;
	table
//  Y  S0 S1 S2  D
	0 b b b : 0;
	1 0 0 0 : 1;
	1 0 0 1 : 0;
	1 0 1 0 : 0;
	1 0 1 1 : 0;
	1 1 0 0 : 0;
	1 1 0 1 : 0;
	1 1 1 0 : 0;
	1 1 1 1 : 0;
	endtable
endprimitive

primitive DemuxD1(D, Y, S0, S1, S2);
	input Y, S0, S1, S2;
	output D;
	table
//  Y  S0 S1 S2  D
	0 b b b : 0;
	1 0 0 0 : 0;
	1 0 0 1 : 1;
	1 0 1 0 : 0;
	1 0 1 1 : 0;
	1 1 0 0 : 0;
	1 1 0 1 : 0;
	1 1 1 0 : 0;
	1 1 1 1 : 0;
	endtable
endprimitive

primitive DemuxD2(D, Y, S0, S1, S2);
	input Y, S0, S1, S2;
	output D;
	table
//  Y  S0 S1 S2  D
	0 b b b : 0;
	1 0 0 0 : 0;
	1 0 0 1 : 0;
	1 0 1 0 : 1;
	1 0 1 1 : 0;
	1 1 0 0 : 0;
	1 1 0 1 : 0;
	1 1 1 0 : 0;
	1 1 1 1 : 0;
	endtable
endprimitive

primitive DemuxD3(D, Y, S0, S1, S2);
	input Y, S0, S1, S2;
	output D;
	table
//  Y  S0 S1 S2  D
	0 b b b : 0;
	1 0 0 0 : 0;
	1 0 0 1 : 0;
	1 0 1 0 : 0;
	1 0 1 1 : 1;
	1 1 0 0 : 0;
	1 1 0 1 : 0;
	1 1 1 0 : 0;
	1 1 1 1 : 0;
	endtable
endprimitive

primitive DemuxD4(D, Y, S0, S1, S2);
	input Y, S0, S1, S2;
	output D;
	table
//  Y S0 S1 S2 D
	0 b b b : 0;
	1 0 0 0 : 0;
	1 0 0 1 : 0;
	1 0 1 0 : 0;
	1 0 1 1 : 0;
	1 1 0 0 : 1;
	1 1 0 1 : 0;
	1 1 1 0 : 0;
	1 1 1 1 : 0;
	endtable
endprimitive

primitive DemuxD5(D, Y, S0, S1, S2);
	input Y, S0, S1, S2;
	output D;
	table
//  Y  S0 S1 S2  D
	0 b b b : 0;
	1 0 0 0 : 0;
	1 0 0 1 : 0;
	1 0 1 0 : 0;
	1 0 1 1 : 0;
	1 1 0 0 : 0;
	1 1 0 1 : 1;
	1 1 1 0 : 0;
	1 1 1 1 : 0;
	endtable
endprimitive

primitive DemuxD6(D, Y, S0, S1, S2);
	input Y, S0, S1, S2;
	output D;
	table
//  Y  S0 S1 S2  D
	0 b b b : 0;
	1 0 0 0 : 0;
	1 0 0 1 : 0;
	1 0 1 0 : 0;
	1 0 1 1 : 0;
	1 1 0 0 : 0;
	1 1 0 1 : 0;
	1 1 1 0 : 1;
	1 1 1 1 : 0;
	endtable
endprimitive

primitive DemuxD7(D, Y, S0, S1, S2);
	input Y, S0, S1, S2;
	output D;
	table
//  Y  S0 S1 S2  D
	0 b b b : 0;
	1 0 0 0 : 0;
	1 0 0 1 : 0;
	1 0 1 0 : 0;
	1 0 1 1 : 0;
	1 1 0 0 : 0;
	1 1 0 1 : 0;
	1 1 1 0 : 0;
	1 1 1 1 : 1;
	endtable
endprimitive

module exercise4_1;
	reg Y, A, B, C;
	wire [7:0]X;
	
	DemuxD0 (X[0],Y,A,B,C);
	DemuxD1 (X[1],Y,A,B,C);
	DemuxD2 (X[2],Y,A,B,C);
	DemuxD3 (X[3],Y,A,B,C);
	DemuxD4 (X[4],Y,A,B,C);
	DemuxD5 (X[5],Y,A,B,C);
	DemuxD6 (X[6],Y,A,B,C);
	DemuxD7 (X[7],Y,A,B,C);
	
	initial begin
		#2 Y=1&#39;b0; A=1&#39;b0; B=1&#39;b0; C=1&#39;b0;
		$display(&quot;&quot;);
		$display(&quot;         8x1 Demultiplexer Truth Table&quot;);
		$display(&quot;&quot;);
		$display(&quot; Y   S1  S2  S3  D0  D1  D2  D3  D4  D5  D6  D7 &quot;);
		$monitor(&quot; %b   %b   %b   %b   %b   %b   %b   %b   %b   %b   %b   %b &quot;, Y, A, B, C, X[0], X[1], X[2], X[3], X[4], X[5], X[6], X[7]);
		#2 Y=1&#39;b0; A=1&#39;b0; B=1&#39;b0; C=1&#39;b1;
		#2 Y=1&#39;b0; A=1&#39;b0; B=1&#39;b1; C=1&#39;b0;
		#2 Y=1&#39;b0; A=1&#39;b0; B=1&#39;b1; C=1&#39;b1;
		#2 Y=1&#39;b0; A=1&#39;b1; B=1&#39;b0; C=1&#39;b0;
		#2 Y=1&#39;b0; A=1&#39;b1; B=1&#39;b0; C=1&#39;b1;
		#2 Y=1&#39;b0; A=1&#39;b1; B=1&#39;b1; C=1&#39;b0;
		#2 Y=1&#39;b0; A=1&#39;b1; B=1&#39;b1; C=1&#39;b1;
		#2 Y=1&#39;b1; A=1&#39;b0; B=1&#39;b0; C=1&#39;b0;
		#2 Y=1&#39;b1; A=1&#39;b0; B=1&#39;b0; C=1&#39;b1;
		#2 Y=1&#39;b1; A=1&#39;b0; B=1&#39;b1; C=1&#39;b0;
		#2 Y=1&#39;b1; A=1&#39;b0; B=1&#39;b1; C=1&#39;b1;
		#2 Y=1&#39;b1; A=1&#39;b1; B=1&#39;b0; C=1&#39;b0;
		#2 Y=1&#39;b1; A=1&#39;b1; B=1&#39;b0; C=1&#39;b1;
		#2 Y=1&#39;b1; A=1&#39;b1; B=1&#39;b1; C=1&#39;b0;
		#2 Y=1&#39;b1; A=1&#39;b1; B=1&#39;b1; C=1&#39;b1;
		#200 $finish;
	end
endmodule</code></pre>


<br /><br />


<h5>Drill4_2</h5>
<pre class="line-numbers"><code class="lang-verilog">primitive Diff(D, A, B, Bin);
	input A, B, Bin;
	output D;
	table
//  A B Bin D
	0 0 0 : 0;
	0 0 1 : 1;
	0 1 0 : 1;
	0 1 1 : 0;
	1 0 0 : 1;
	1 0 1 : 0;
	1 1 0 : 0;
	1 1 1 : 1;
	endtable
endprimitive

primitive Bout (Bout, A, B, Bin);
	input A, B, Bin;
	output Bout;
	table
//	A B Bin Bout
	0 0 0 : 0;
	0 0 1 : 1;
	0 1 0 : 1;
	0 1 1 : 1;
	1 0 0 : 0;
	1 0 1 : 0;
	1 1 0 : 0;
	1 1 1 : 1;
	endtable
endprimitive

module exercise4_2;
	reg A, B, Bin;
	wire [1:0] D;
	
	Diff (D[0], A, B, Bin);
	Bout (D[1], A, B, Bin);
	
	initial begin
		#2 A=1&#39;b0; B=1&#39;b0; Bin=1&#39;b0;
		$display(&quot;&quot;);
		$display(&quot;         Full Binary Subtrator&quot;);
		$display(&quot;&quot;);
		$display(&quot;          A  B  Bin  Diff  Bout  &quot;);
		$monitor(&quot;          %b  %b  %b    %b     %b&quot;, A, B, Bin, D[0], D[1]);
		#2 A=1&#39;b0; B=1&#39;b0; Bin=1&#39;b1;
		#2 A=1&#39;b0; B=1&#39;b1; Bin=1&#39;b0;
		#2 A=1&#39;b0; B=1&#39;b1; Bin=1&#39;b1;
		#2 A=1&#39;b1; B=1&#39;b0; Bin=1&#39;b0;
		#2 A=1&#39;b1; B=1&#39;b0; Bin=1&#39;b1;
		#2 A=1&#39;b1; B=1&#39;b1; Bin=1&#39;b0;
		#2 A=1&#39;b1; B=1&#39;b1; Bin=1&#39;b1;
		#2 $finish;
	end
endmodule</code></pre>


<br /><br />


<p>Laboratory Report:  <a href="https://drive.google.com/file/d/1F6YQvZfsv5gTPcGfXwDsKr6PIHucC0OK/view?usp=sharing" target="_blank">Click here to download the file</a></p>

Experiment 4

<h5>Drill5_1</h5>
<pre class="lang-verilog line-numbers"><code>module flip_flop (clk, reset, d, q); input clk, reset, d; output q; 
reg q; 
 
always @ (posedge clk ) begin 
if (reset == 1)  begin q &lt;= 0; 
end 
else  begin q &lt;= d; 
end 
end 
endmodule 
module circuit_ff(input clk, reset, x, output y); 
 	wire OR1, OR2, AND1, AND2, AND3;  	wire A, B, Bnot; 
 	not (Bnot, B); 
 	flip_flop ff1(clk, reset, OR1, A);  	flip_flop ff2(clk, reset, OR2, B); 
 	and (AND1,A,x), (AND2,B,x), (AND3,Bnot,x), (AND4,A,B); 
 	or (OR1, AND1,AND2), (OR2,AND1,AND3);  	and (y,B,A); 
endmodule 
 
module drill5_1; 
 	reg clk, reset,d;  	wire q; 
 	circuit_ff cff(clk, reset, d, q); 
 	 	 
 	initial begin 
 	 	 	clk=0; reset=1; d=0; 
 	 	 	$monitor(&quot;clk=%b reset=%b d=%b q=%b&quot;,clk,reset,d,q); 
 	end 
 	initial begin  	 	forever #1 clk=~clk; 
 	end 
 	initial fork 
 	 	#1 reset=0; 
 	 	#2 d=1; 
 	 	#3 reset=1; 
 	 	#4 reset=0; 
 	 	#5 d=0; 
 	 	#8 d=1; 
 	 	#10 $finish;  	join 
endmodule</code></pre>


<br /><br />


<h5>Drill5_2</h5>
<pre class='lang-verilog line-numbers'><code>module mux_8_1 (output reg m_out, input [7:0]in_x, input[2:0] select); 
 	always@(in_x[0],in_x[1],in_x[2],in_x[3],in_x[4],in_x[5],in_x[6],in_x[7],select
) 
 	case(select) 
 	3&#39;b000: m_out=in_x[0];  
 	3&#39;b001: m_out=in_x[1]; 
 	3&#39;b010: m_out=in_x[2]; 
 	3&#39;b011: m_out=in_x[3]; 
 	3&#39;b100: m_out=in_x[4]; 
 	3&#39;b101: m_out=in_x[5]; 
 	3&#39;b110: m_out=in_x[6]; 
 	3&#39;b111: m_out=in_x[7];  	endcase 
endmodule 
 
module drill5_2();  	reg [7:0] x;  	reg [2:0] select; 
 	wire m_out; 
 	 
 mux_8_1 MUX1(m_out, x, select);  initial begin 
 	  	select=2&#39;b00; x=8&#39;h4F;  	 	$strobe(&quot;Select Input Output&quot;); 
 	 	$monitorb(select,&quot;    &quot;, x, &quot;   &quot;, m_out); 
 	 	#1 select=3&#39;b000; 
 	 	#1 select=3&#39;b001; 
 	 	#1 select=3&#39;b010; 
 	 	#1 select=3&#39;b011; 
 	 	#1 select=3&#39;b100; 
 	 	#1 select=3&#39;b101; 
 	 	#1 select=3&#39;b110; 
 	 	#1 select=3&#39;b111; 
	 	#1 $display(&quot;Changing value of input&quot;); 
 	 	#1 x=8&#39;h98; 
 	 	#1 select=3&#39;b000; 
 	 	#1 select=3&#39;b001; 
 	 	#1 select=3&#39;b010; 
 	 	#1 select=3&#39;b011; 
 	 	#1 select=3&#39;b100; 
 	 	#1 select=3&#39;b101; 
 	 	#1 select=3&#39;b110; 
 	 	#1 select=3&#39;b111;  	 
 	 	#100 $finish;  	
end 
endmodule</code></pre>


<br /><br />


<h5>Drill5_3</h5>
<pre class="line-numbers lang-verilog"><code >module state_diagram(  	output reg y_out,   	input x_in, clock, reset ); 
 
 	reg[1:0] state, next_state;  	parameter S0=2&#39;b00, 
 	 	  S1=2&#39;b01, 
 	 	  S2=2&#39;b10,  	 	  S3=2&#39;b11; 
 	always@(posedge clock, negedge reset)  	 	if (reset==0) state &lt;= S0;  	 	else state &lt;= next_state; 
 	always@(state, x_in)  	 	case (state) 
 	 	S0: 	if (x_in) next_state=S1; else next_state=S0; 
 	 	S1: 	if (x_in) next_state=S3; else next_state=S0; 
 	 	S2: 	if (~x_in) next_state=S0; else next_state=S2;  	 	S3: 	if (x_in) next_state=S2; else next_state=S0; 
 	 	endcase 
 	always@(state, x_in)  	 	case (state) 
 	 	S0: 	 	y_out=0; 
 	 	S1,S2,S3: 	y_out=~x_in; 
 	 	endcase 
endmodule 
 
module drill5_3; 
 	wire t_y_out; 
 	reg t_x_in, t_clock, t_reset; 
 	state_diagram 	sd(t_y_out, t_x_in, t_clock, t_reset);  	initial #200 $finish;  	initial begin  
 	 	t_clock=0; 
 	 	forever #5 t_clock=~t_clock; 
 	 
 	end 
 	initial fork 
 $monitor($time,,&quot;reset=%b clock=%b x=%b y=%b&quot; ,t_reset, t_clock, t_x_in, t_y_out); 
 	 	t_reset=0; 
 	#2 	t_reset=1; 
 	#87 	t_reset=0; 
 	#89 	t_reset=1; 
 	#10 	t_x_in=1; 
 	#30 	t_x_in=0; 
 	#40 	t_x_in=1; 
 	#50 	t_x_in=0; 
 	#52 	t_x_in=1; 
 	#54 	t_x_in=0; 
 	#70 	t_x_in=1; 
 	#80 	t_x_in=1; 
 	#70 	t_x_in=0; 
 	#90 	t_x_in=1; 
 	#100 t_x_in=0; 
 	#120 t_x_in=1; 
 	#160 t_x_in=0; 
 	#170 t_x_in=1;  	join 
endmodule</code></pre>


<br /><br />


<h5>Exercise5_1</h5>
<pre class='lang-verilog line-numbers'><code>module t_flip_flop(clk, reset, t_in, t_out);
	input clk, reset, t_in;
	output t_out;
	reg t_out;

	always @ (negedge clk)
	begin
		if(reset == 1)
		begin
			t_out &lt;= 0;
		end
		else if (t_in == 1)
		begin
			t_out &lt;= ~t_out;
		end
		else
		begin
			t_out &lt;= t_out;
		end
	end
endmodule

module circuit_tff(input clk, reset, x, output [2:0]t_out);
	wire clk1, clk2;
	t_flip_flop tff0(clk, reset, x, clk1);
	buf bf1(t_out[0], clk1);
	t_flip_flop tff1(clk1, reset, x, clk2);
	buf bf2(t_out[1], clk2);
	t_flip_flop tff2(clk2, reset, x, t_out[2]);

endmodule

module exercise5_1;
	reg clk, rst, t_in;
	wire [2:0] t_out;
	circuit_tff ctff(clk, rst, t_in, t_out);

	initial begin
		clk=0; rst=1; t_in=0;
		$monitor(&quot;clk = %b rst = %b ctr_state = %b%b&quot;, clk, rst, t_out, clk);
	end
	initial begin
		forever #1 clk = ~clk;
	end
	initial fork
		#1 rst = 0;
		#2 t_in = 1;
		#16 $finish;
	join
endmodule
</code></pre>


<br /><br />


<h5>Exercise5_2</h5>
<pre class="line-numbers"><code class="lang-verilog">module JKFF(input clk, reset,J,K, output reg Q);
 	initial Q=0;
 	always @(posedge clk)
 	begin
 		if(reset ==1)
 		begin
 			Q&lt;=0;
 		end	
 		else
 		begin
 			if(J==0&amp;&amp;K==0)
 			Q&lt;=Q;
 			else
 			begin
 				if(J==1&amp;&amp;K==0)
 				Q&lt;=1;
 				else
 					begin
 					if(J==1&amp;&amp;K==1)
 					Q&lt;=~Q;
 					end
 				end
 			end
 		end
endmodule

module circuit(input clk, reset, X, Y, output F1, F2);
	//input clk, reset, X, Y;
	//output F1,F2;
	wire Xnot;
	wire [3:0] eor;
	wire J1, J2, K1, K2;
	wire A, B;

	not M1(Xnot,X);
	xor M2(eor[3],Y,F2), M3(eor[0],Y,F1);
	xnor M4(eor[2],Y,F2), M5(eor[1],Y,F1);
	and M6(J1,Xnot,eor[3]), M7(K1,Xnot, eor[2]), M8(J2,Xnot,eor[1]), M9(K2,Xnot,eor[0]);

	JKFF jkff1(clk, reset, J1,K1,A);
	JKFF jkff2(clk, reset, J2,K2,B);

	buf(F1,A);
	buf(F2,B);
	endmodule

module exercise5_2;
	reg clk, reset, J,K,A,B;
	wire F1, F2;
	circuit ckt1(clk, reset, A,B,F1,F2);

	initial
	begin
	clk=0; reset =0;
	$display(&quot;\t           T CLK  A B F1 F2&quot;);
	end

	initial begin
	$monitor ($time,,,&quot;%b   %b %b %b  %b &quot;,clk,A,B,F1,F2);
	end

	always #1 clk=!clk;

	initial begin
	A = 1&#39;b0; B = 1&#39;b0;
	#8 A = 1&#39;b0; B = 1&#39;b1;
	#8 A = 1&#39;b1; B = 1&#39;b0;
	#8 A = 1&#39;b1; B = 1&#39;b1;
	#8 $finish;
	end
endmodule</code></pre>


<br /><br />


<h5>Exercise5_3</h5>
<pre class="line-numbers"><code class="lang-verilog">module flip_flop(clk,reset,d,q);
	input clk, reset,d;
	output q;
	reg q;
	initial begin
	q=0;
end
	always@(posedge clk)
	begin
	if(reset==1)
	begin
	q<=0;
	end
	else
	begin
	q<=d;
	end
	end
endmodule

module mux_4_1(output reg m_out, input IN0,IN1, IN2, IN3, input[1:0] select);
	always@(IN0, IN1, IN2, IN3, select)
	case(select)
	2'b00:m_out=IN0;
	2'b01:m_out=IN1;
	2'b10:m_out=IN2;
	2'b11:m_out=IN3;
	endcase
endmodule

module circuit_ff(input clk, reset, input[3:0] U, input[1:0] sel, output T3, T2,T1,T0);
	wire A,B,C,D,O1,O2,O3,O4, zero1;
	buf (zero1,0);
	flip_flop ff1(clk,reset,O1,A);
	flip_flop ff2(clk,reset,O2,B);
	flip_flop ff3(clk,reset,O3,C);
	flip_flop ff4(clk,reset,O4,D);

	mux_4_1 mux1(O1,A,B,U[3],B,sel);
	mux_4_1 mux2(O2,B,C,U[2],C,sel);
	mux_4_1 mux3(O3,C,D,U[1],D,sel);
	mux_4_1 mux4(O4,D,zero1,U[0],zero1,sel);

	buf(T3,A);
	buf(T2,B);
	buf(T1,C);
	buf(T0,D);
endmodule

module exercise5_3();
	reg clk,reset;
	reg[3:0] U;
	reg[1:0] select;
	wire OUT3, OUT2,OUT1,OUT0;

	circuit_ff circ(clk, reset, U, select, OUT0, OUT1,OUT2,OUT3);
	initial begin
	select=2'b00;
	U=8'hAF;
	reset=0;
	clk=0;
	$strobe("clk  sel    in     out");
	$monitorb(clk, "    ", select, "    ", U, "    ", OUT0, OUT1,OUT2,OUT3);
	#1 select=2'b01;
	#1 select=2'b01;
	#1 select=2'b10;
	#1 select=2'b10;
	#1 select=2'b11;
	#1 select=2'b11;
	#1 select=2'b00;
	#1 select=2'b01;
	#1 select=2'b10;
	#1 select=2'b01;
	#1 select=2'b10;
	#1 select=2'b11;
	#10 $finish;
	end
	initial begin
	forever #1 clk=~clk;
	end
endmodule</code></pre>


<br /><br />


<p>Laboratory Report:  <a href="https://drive.google.com/file/d/1oPo2mBGoikEZp_GqM5HPXETVlMqZn-xy/view?usp=sharing" target="_blank">Click here to download the file</a></p>

Experiment 5

<h5>Drill6_1</h5>
<pre class='line-numbers lang-verilog'><code>module magcom (input [3:0] A, B, output lt, gt, eq);
	assign lt=(A&lt;B);
	assign gt=(A&gt;B);
	assign eq=(A==B);
endmodule

module drill6_1;
	reg [3:0] A, B;
	wire lt, gt, eq;
	magcom tb(A, B, lt, gt, eq);
	reg [255:0]string1, string2, string3;
	
	initial fork
		A=1&#39;b0; B=1&#39;b0;
		$display(&quot; A B \t\t\t\t A&lt;B \t\t \t\t A&gt;B\t\t\t\t A==B&quot;);
		$monitor(&quot;%d %d %s %s %s&quot;,A, B, string1, string2, string3);
	join
	initial begin
		#1 A=4&#39;d7;
		B=4&#39;d7;
		if (lt==1) string1=&quot;true&quot;;
		else string1=&quot;false&quot;;
		if (gt==1) string2=&quot;true&quot;;
		else string2=&quot;false&quot;;
		if (eq==1) string3=&quot;true&quot;;
		else string3=&quot;false&quot;;
		#3 A=4&#39;d4;
		B=4&#39;d6;
		if (lt==1) string1=&quot;true&quot;;
		else string1=&quot;false&quot;;
		if (gt==1) string2=&quot;true&quot;;
		else string2=&quot;false&quot;;
		if (eq==1) string3=&quot;true&quot;;
		else string3=&quot;false&quot;;
		#5 A=4&#39;d9;
		B=4&#39;d8;
		if (lt==1) string1=&quot;true&quot;;
		else string1=&quot;false&quot;;
		if (gt==1) string2=&quot;true&quot;;
		else string2=&quot;false&quot;;
		if (eq==1) string3=&quot;true&quot;;
		else string3=&quot;false&quot;;
		#7 A=4&#39;d10;
		B=4&#39;d1;
		if (lt==1) string1=&quot;true&quot;;
		else string1=&quot;false&quot;;
		if (gt==1) string2=&quot;true&quot;;
		else string2=&quot;false&quot;;
		if (eq==1) string3=&quot;true&quot;;
		else string3=&quot;false&quot;;
		#9 $finish;
	end
endmodule</code></pre>


<br /><br />


<h5>Drill6_2</h5>
<pre class='line-numbers lang-verilog'><code>module AllBit(input [31:0]x, output zero, one);
	assign zero=~(|x);
	assign one=&amp;x;
endmodule

module drill6_2;
	reg [31:0] inputX;
	wire outputZ, outputO;
	
	AllBit Abit(inputX, outputZ, outputO);
	initial fork
		$monitor($time,,,&quot; %h&quot;,inputX,&quot; %h&quot;,outputO,&quot; %h&quot;,outputZ);
		inputX=32&#39;h0;
		#1 inputX=32&#39;h12345678;
		#2 inputX=0;
		#3 inputX=32&#39;hFFFFFFFF;
		#4 inputX=32;
		#4 $finish;
	join
endmodule</code></pre>


<br /><br />


<h5>Drill6_3</h5>
<pre class='line-numbers lang-verilog'><code>module JK_flipflop(output A, input J, K, clk, reset);
	wire AofJK;
	assign AofJK=(J&amp;~A)|(~K&amp;A);
	D_flipflop JKf(A,AofJK,clk, reset);
endmodule

module D_flipflop(output reg B, input D, clk, reset);
	always@(posedge clk, negedge reset)
	begin
		if(~reset)
			B&lt;=1&#39;b0;
		else
			B&lt;=D;
	end
endmodule

module drill6_3;
	reg J, K, clk, reset;
	wire Q;
	always #1 clk=~clk;
	
	JK_flipflop JKF(Q,J,K,clk,reset);
	
	initial clk=0;
	initial reset=0;
	initial J=0;
	initial K=0;
	initial $monitor(&quot;clk=%b reset=%b, J=%b, K=%b, Q=%b&quot;,clk,reset,J,K,Q);

	initial fork
		#28 $finish;
		#2 reset=1;
		#4 J=1;
		#8 K=1;
		#12 J=0;
		#16 K=0;
		#20 J=1;
		#24 J=0;
	join
endmodule</code></pre>


<br /><br />


<h5>Exercise6_1</h5>
<pre class='line-numbers lang-verilog'><code>module checkCntr(disp, A, B);
	output reg [255:0] disp;
	input [7:0] A, B;
	reg [7:0] tmpA, tmpB;
	integer Acnt, Bcnt;
	wire gthan, lthan, eqls;

	always @(A, B) begin
		Acnt=0; Bcnt=0;
		tmpA=A; tmpB=B;
		repeat (8) begin
			Acnt = Acnt + tmpA[0];
			Bcnt = Bcnt + tmpB[0];
			tmpA = tmpA &gt;&gt; 1;
			tmpB = tmpB &gt;&gt; 1;
		end
		if(gthan) disp=&quot;&gt;&quot;;
		else if(lthan) disp=&quot;&lt;&quot;;
		else disp=&quot;=&quot;;
	end

	assign gthan = (Acnt &gt; Bcnt);
	assign lthan = (Acnt &lt; Bcnt);
	assign eqls = (Acnt == Bcnt);
endmodule

module exercise6_1;
	reg [7:0] A, B;
	wire [255:0] disp;

	checkCntr tb(disp, A, B);

	initial begin
	A=0; B=0;
	$display(&quot;\n Comparing 8-bit input A &amp; B\n&quot;);
	$display(&quot;\t    A         B              Comparison &quot;);
	$monitor(&quot;\t %b  %b      %b %0s %b        &quot;, A, B, A, disp, B);
	#2 A=8&#39;d64; B=8&#39;d31;
	#2 A=8&#39;d21; B=8&#39;d129;
	#2 A=8&#39;d224; B=8&#39;d7;
	#2 A=8&#39;d2; B=8&#39;d7;
	#2 A=8&#39;d9; B=8&#39;d2;
	#2 $finish;
	end
endmodule</code></pre>


<br /><br />


<h5>Exercise6_2</h5>
<pre class='line-numbers lang-verilog'><code>module counter(A, B, C, clk);
	output A, B, C;
	input clk;
	reg Ta, Tb, Tc;

	T_FF Q2(A, Ta, clk, 1&#39;h1);
	T_FF Q1(B, Tb, clk, 1&#39;h0);
	T_FF Q0(C, Tc, clk, 1&#39;h1);

	always @(clk) begin
		Ta=(~B&amp;C)|(A&amp;C)|(~A&amp;B&amp;~C);
		Tb=A|~B|C;
		Tc=A|~B|~C;
	end
endmodule

module T_FF(Q, Tin, clk, startVal);
	output reg Q;
	input Tin, clk, startVal;
	wire T;
	
	initial Q=startVal;

	assign T=Q^Tin;

	always @(posedge clk) begin
		Q=T;
	end
endmodule

module exercise6_2;
	wire [2:0] Q;
	reg clk;

	counter testb(Q[2], Q[1], Q[0], clk);
	
	always #2 clk=~clk;	

	initial begin
	clk=0;
	$display(&quot;\n       T flip-flop Counter&quot;);
	$display(&quot;\n    Sequence: 5-2-7-0-3-1-6-5\n&quot;);
	$display(&quot;             XYZ Val&quot;);
	$monitor(&quot;             %b  %d&quot;, Q, Q);
	#40 $finish;
	end
endmodule</code></pre>


<br /><br />


<p>Laboratory Report:  <a href="https://drive.google.com/file/d/1oPo2mBGoikEZp_GqM5HPXETVlMqZn-xy/view?usp=sharing" target="_blank">Click here to download the file</a></p>

Experiment 6

<h5>Drill7_1</h5>
<pre class="line-numbers lang-verilog"><code>module task1 (temp_a, temp_b, temp_c, temp_d);
	input [7:0] temp_a, temp_c;
	output [7:0] temp_b, temp_d;
	reg [7:0] temp_b, temp_d;
	initial temp_b=0;
	task convert;
		input [7:0] temp_in;
		output [7:0] temp_out;
		begin
		temp_out = ((9*temp_in)/5)+32;
		end
	endtask
	always@(temp_a or temp_b or temp_c or temp_d)
	begin
		convert (temp_a,temp_b);
		convert (temp_c,temp_d);
	end
endmodule

module drill7_1;
	reg [7:0]temp_a, temp_c;
	wire [7:0]temp_b, temp_d;
	task1 t1(temp_a,temp_b,temp_c,temp_d);
	
	initial begin
		#1 temp_a=8&#39;d0; temp_c=8&#39;d32;
		#2 $display(&quot;Temperature A in Celsius = %d&quot;,temp_a);
		#2 $display(&quot;Temperature A in Fahrenheit = %d&quot;, temp_b);
		#2 $display(&quot;Temperature B in Celsius = %d&quot;,temp_c);
		#2 $display(&quot;Temperature B in Fahrenheit = %d&quot;, temp_d);
	end
endmodule</code></pre>


<br /><br />


<h5>Drill7_2</h5>
<pre class="line-numbers lang-verilog"><code>module drill7_2;
	function automatic [31:0] calFactorial;
	input [7:0] number;
	begin
		if (number == 1) begin
			calFactorial=1;
		end
		else begin
			calFactorial=number*calFactorial(number-1);
		end
	end
	endfunction
	
	initial begin
		$display(&quot;Factorial of 1:%d&quot;, calFactorial(1));
		$display(&quot;Factorial of 2:%d&quot;, calFactorial(2));
		$display(&quot;Factorial of 16:%d&quot;, calFactorial(16));
	end
endmodule</code></pre>


<br /><br />


<h5>Drill7_3</h5>
<pre class="line-numbers lang-verilog"><code>primitive mem(D,A,B,C);
	input A,B,C;
	output D;
	table
	 // A B C : D
		0 0 0 : 1;
		0 0 1 : 0;
		0 1 0 : 0;
		0 1 1 : 1;
		1 0 0 : 1;
		1 0 1 : 0;
		1 1 0 : 1;
		1 1 1 : 1;
	endtable
endprimitive

module drill7_3;
	integer fileno;
	reg [255:0] mem[0:255];
	reg A,B,C;
	wire D;
	integer x;
	reg [255:0] data;
	initial x=0;
	
	mem (D,A,B,C);
	initial begin
//Disregard older syntax shown to you during discussion
//Use the following syntax instead
//file handle is fileno, and “memory.txt” is the file to be opened
//memory.txt is expected to be saved within the current working directory of
//drill7_3.vl.
		fileno=$fopen(&quot;memory.txt&quot;);
		A=1&#39;B0; B=1&#39;B0; C=1&#39;B0;
		#1 $display(&quot;Saving truth table to file...&quot;);
		#1 $fdisplay(fileno,&quot;%b%b%b%b&quot;,A,B,C,D);
		#1 A=1&#39;B0; B=1&#39;B0; C=1&#39;B1;
		#1 $fdisplay(fileno,&quot;%b%b%b%b&quot;,A,B,C,D);
		#1 A=1&#39;B0; B=1&#39;B1; C=1&#39;B0;
		#1 $fdisplay(fileno,&quot;%b%b%b%b&quot;,A,B,C,D);
		#1 A=1&#39;B0; B=1&#39;B1; C=1&#39;B1;
		#1 $fdisplay(fileno,&quot;%b%b%b%b&quot;,A,B,C,D);
		#1 A=1&#39;B1; B=1&#39;B0; C=1&#39;B0;
		#1 $fdisplay(fileno,&quot;%b%b%b%b&quot;,A,B,C,D);
		#1 A=1&#39;B1; B=1&#39;B0; C=1&#39;B1;
		#1 $fdisplay(fileno,&quot;%b%b%b%b&quot;,A,B,C,D);
		#1 A=1&#39;B1; B=1&#39;B1; C=1&#39;B0;
		#1 $fdisplay(fileno,&quot;%b%b%b%b&quot;,A,B,C,D);
		#1 A=1&#39;B1; B=1&#39;B1; C=1&#39;B1;
		#1 $fdisplay(fileno,&quot;%b%b%b%b&quot;,A,B,C,D);
		#1 $fclose(fileno);
		#1 $display(&quot;Retrieving truth table from file..&quot;);
		#1 $readmemb(&quot;memory.txt&quot;,mem);
		#1 while (x!=8)
			begin
				data=mem[x];
				$display(&quot;%b %b %b : %b&quot;, data[3], data[2], data[1], data[0]);
				x=x+1;
			end
	end
endmodule</code></pre>


<br /><br />


<h5>Drill7_4</h5>
<pre class="line-numbers lang-verilog"><code>module drill7_4;

task borderopen;
begin
	$display(&quot;****************************************************&quot;);
	repeat(8)
	$display(&quot;***                                              ***&quot;);
end
endtask

task borderclose;
begin
	repeat(8)
	$display(&quot;***                                              ***&quot;);
	$display(&quot;****************************************************&quot;);
end
endtask

	reg [3:0]x;
	initial begin
		$monitor(&quot;\t\t\t&quot;,x);
		#1 borderopen;
		#1 $display(&quot;\t This is a set of random values\n&quot;);
		repeat (4)
		#1 x=$random;
		#1 borderclose;
		#1 $stop;
		#1 borderopen;
		#1 $display(&quot;\tThis is a new set of random values\n&quot;);
		repeat (4)
		#1 x=$random;
		#1 borderclose;
		#1 $stop;
		#20 $finish;
	end
endmodule</code></pre>


<br /><br />


<h5>Exercise7_1</h5>
<pre class="line-numbers lang-verilog"><code>module operation(inX, X, n, disp, Q);
	input [3:0] inX;
	output reg [3:0] Q;
	input X;
	input [3:0] n;
	reg [3:0] ntmp;
	reg tmpN;
	integer fileHandle;
	reg [255:0] mem [0:255];
	output reg [255:0] disp;

	initial Q=0;

	always @(X, n, inX) begin
		ntmp = n;
		if(X==1) begin
			Q = inX;
			fileHandle = $fopen(&quot;exercise7_1.txt&quot;);
			while(ntmp!=0) begin
				Q = Q + 1;
				ntmp = ntmp-1;
			end
			disp=&quot;Do Increment and then Save  |&quot;;
			$fwrite(fileHandle, &quot;%b&quot;, Q);
			$fclose(fileHandle);
		end
		else begin
			mem[0] = 0;
			disp=&quot;Do Read, Rotate, and Update |&quot;;
			$readmemb(&quot;exercise7_1.txt&quot;, mem, mem[0], mem[3]);
			Q = mem[0];
			repeat(ntmp) begin
				tmpN = Q[3];
				Q = Q &lt;&lt; 1;
				Q[0] = tmpN;
			end
			fileHandle = $fopen(&quot;exercise7_1.txt&quot;);
			$fwrite(fileHandle, &quot;%b&quot;, Q);
			$fclose(fileHandle);
		end
	end
endmodule

module exercise7_1;
	reg [3:0] inX;
	reg X;
	reg [3:0] n;
	wire [3:0] Q;
	wire [255:0] disp;

	operation tb(inX, X, n, disp, Q);

	initial begin
	X=1; n=1; inX=2;
	$display(&quot;       _________________________________________________________________________ &quot;);
	$display(&quot;      |                                                                         |&quot;);
	$display(&quot;      |                           4-Bit Circulation                             |&quot;);
	$display(&quot;      |                                                                         |&quot;);
	$display(&quot;      |       Operations:                                                       |&quot;);
	$display(&quot;      |       If X=0, Do Read from txt file then rotate to left it n times      |&quot;);
	$display(&quot;      |       If X=1, Do Increment data it n times and save to txt file         |&quot;);
	$display(&quot;      |       Legend: D - Decimal, B - Binary                                   |&quot;);
	$display(&quot;      |_________________________________________________________________________|&quot;);
	$display(&quot;      |   |   |                  |                |                             |&quot;);
	$display(&quot;      | X | n |  inX(D)   inX(B) | Out(D) Out(B)  |             Msg             |&quot;);
	$monitor(&quot;      | %b |%d |   %d       %b  |  %d     %b   | %0s&quot;, X, n, inX, inX, Q, Q, disp);
	#2 X=0; n=3;
	#2 X=1; n=5; inX=4;
	#2 X=0; n=3;
	#2 X=1; n=5; inX=6;
	#2 X=0; n=1;
	#2 $display(&quot;      |___|___|__________________|________________|_____________________________|&quot;);
	#2 $finish;
	
	end
endmodule</code></pre>


<br /><br />


<h5>Exercise7_2</h5>
<pre class="line-numbers lang-verilog"><code>module exercise7_2();
function automatic [31:0] product;
	input [7:0] num1;
	input [7:0] num2;
 
	begin
  
		if(num2 &gt; 0)
		begin 
			product = num1 + product(num1, num2-1);
			end
		else
		begin
			product = 0;
		end  
	end
endfunction
 
	initial begin
		$display(&quot;    ____________________________________________________ &quot;);
		$display(&quot;   |                                                    |&quot;);
		$display(&quot;   |       Multiplication using Recursive Addition      |&quot;);
		$display(&quot;   |____________________________________________________|&quot;);
		$display(&quot;   |                  |              |                  |&quot;);
		$display(&quot;   |   Multiplicand   |  Multiplier  |     Product      |&quot;);
		$display(&quot;   |        5         |      4       |%d&quot;, product(5,4), &quot;        |&quot;);
		$display(&quot;   |        7         |      2       |%d&quot;, product(7,2), &quot;        |&quot;);
		$display(&quot;   |        8         |      3       |%d&quot;, product(8,3), &quot;        | &quot;);
		$display(&quot;   |__________________|______________|__________________|&quot;);
		$display(&quot;&quot;);
	end
endmodule </code></pre>


<br /><br />


<p>Laboratory Report:  <a href="https://drive.google.com/file/d/1Yd2LyHUEGw8ViDPWxHc0Kop-sARHCaTC/view?usp=sharing" target="_blank">Click here to download the file</a></p>

Experiment 7

<p><i>Since this experiment was mostly installation of needed softwares and tools. It does not contain any codes. So, I'll just provide the Laboratory Report.</i></p>
<p><a target="_blank" href="https://drive.google.com/file/d/1GERu91i_XTBjg8GR5e6zgpQr22J_iOW2/view?usp=sharing">Click here to download</a></p>

CPE106L

Laboratory Experiment 1

Programming Paradigms/Object Oriented Design

<h5><b>Prelab</b></h5>
<p>3. Class B extends class A. Class B defines an _str_ method that returns the string representation of its instance variables. Class B defines a single instance variable named age, which is an integer. Write the code to define the _str_ method for class B. This method should return the combined string information from both classes. Label the data for age with the string "Age: ".</p>
<pre class="line-numbers lang-python"><code>class A:
    def __init__(self):
        self.message = &quot;This is from Class A\n&quot;
    
    def __str__(self):
        return self.message


class B(A):
    def __init__(self):
        super().__init__()
        self.age = 18

    def __str__(self):
        return super().__str__() + &quot;Age: &quot; + str(self.age)

b  = B()
print(b)</code></pre>
<br /><br />


<h5><b>Inlab</b></h5>
<p>4. The ATM program allows a user an indefinite number of attempts to log in. Fix the program so that it displays a popup message that the police will be called after a user has had three successive failures. The program should also disable the login button when this happens.</p>
<pre class="line-numbers lang-python"><code># Other codes soon.</code></pre>
<br />


<p>Laboratory Report: <a target="_blank" href="https://drive.google.com/file/d/1fdIjHeCzCTTvgTL_oVeSrWXEr9B8Pfad/view?usp=sharing">Click here to download</a></p>

Laboratory Experiment 2

<h5>6 Bit Subtractor</h5>
<img src="https://i.imgur.com/dkyiSpe.jpg" class="img-fluid w-100" alt="6 bit subtractor"/>
<br /><br />

<h5>Materials used</h5>
<table class="table table-dark table-striped text-center">
<tr class="table-primary">
<th>Name</th>
<th>Quantity</th>
</tr>
<tbody>
<tr><td>6-pin dip switch</td><td>2</td></tr>
<tr><td>7404 IC</td><td>2</td></tr>
<tr><td>7408 IC</td><td>3</td></tr>
<tr><td>7432 IC</td><td>2</td></tr>
<tr><td>7486 IC</td><td>3</td></tr>
<tr><td>LED</td><td>7</td></tr>
<tr><td>330 ohms resistor</td><td>7</td></tr>
<tr><td>10k ohms resistor</td><td>12</td></tr>
<tr><td>Breadboard</td><td>3</td></tr>
<tr><td>Jumper wires</td><td>N/A</td></tr>
</tbody>
</table>

<h5>Logicly Block Diagram</h5>
<img src="https://i.imgur.com/18Y7vOi.png" class="img-fluid  w-100" alt="6 bit subtractor logicly block diagram"/>
<br /><br />

<h5>Logicly Diagram</h5>
<img src="https://i.imgur.com/wxeVgG8.png" class="img-fluid w-100" alt="6 bit subtractor logicly diagram"/>
<br /><br />

<p>Project Documentation:
<a href="https://drive.google.com/file/d/1_68FEJE7JDCMG2gms70ZdepNLf7rj0zu/view?usp=sharing" target="_blank">
Click here to download the file</a>
</p>
<p>Logicly Block Diagram:
<a href="https://drive.google.com/file/d/1aCJgqWi8Y1I5q1QyQHxxgXwQo7vzXJTO/view?usp=sharing" target="_blank">
Click here to download the file</a>
</p>
<p>Logicly Diagram:
<a href="https://drive.google.com/file/d/1uPceXtqMbapP_R6PaI_zsRu_Lz1s6rvD/view?usp=sharing" target="_blank">
Click here to download the file</a>
</p>

CPE111

<p>Sprint 1: <a target="_blank" href="https://drive.google.com/file/d/1M_Afz2KT3m2J-Oag0r4eGkn0jooNG6id/view?usp=sharing">Click here to download</a></p>
<p>Sprint 2: <a target="_blank" href="https://drive.google.com/file/d/1aEATbRWoARCrGWsURoUQtnTrICJ4SMi0/view?usp=sharing">Click here to download</a></p>
<p>Sprint 3: <a target="_blank" href="https://drive.google.com/file/d/1rirWVynccW1JP5x47YoEs9hUNh0u5R9l/view?usp=sharing">Click here to download</a></p>
<p>Sprint 4: <a target="_blank" href="https://drive.google.com/file/d/1xXSgZUJRQDzm_BtzigZJiyEBPdAhXH6H/view?usp=sharing">Click here to download</a></p>

Sprint Reviews

<h5>This is a powerpoint presentation file.</h5><br />
<p>History of Embedded Systems: <a href="https://drive.google.com/file/d/1orxyIDMDZYFLNgupnIF_AdtFxEXESM4J/view?usp=sharing" target="_blank">Download here</a></p>

CPE109

Coursework 1

Examples of Serial and Parallel I/O Communications

<h5>Serial I/O communication</h5><br />
<ol>
<li><strong>Universal Serial Bus (USB)</strong> - This will attach all sorts of external USB devices commonly includes external hard drive, printer and scanner, mouse and keyboard. With USB Type C, computers and smartphones now offer connections to each other.</li>
<li><strong>Ethernet</strong> - provides connection between an end device and a network. It can offer I/O speeds of up to 1000 Megabits per seconds. Some types includes Coaxial, RJ45  and the latest is the Fiber Optic cables.</li>
<li><strong>Peripheral Component Interconnect Express (PCIe)</strong> - Is a standard type of user interface link for internal interfaces like Graphics Processing Units. The PCI Express protocol, as well as other equipment, enables high speed connectivity between devices and motherboard.</li>
<li><strong>Firewire (IEEE 1394)</strong> - Is a standard serial bus interface for high-speed communications and real-time I/O data transmission.</li>
<li><strong>Serial Advanced Technology Attachment Express(SATAe)</strong> - This is an interface which is used to link ATA hard drives to the motherboard of a device. This supports both SATA and PCIe storage devices.</li>
</ol>
<br /><br />

<h5>Parallel I/O communication</h5><br />
<ol>
<li><strong>Parallel port</strong> - The parallel port is located on the back of computers that are compliant with IBM and is a 25-pin (DB-25 type) device interface typically used to link printers to the machine.</li>
<li><strong>Parallel Advanced Technology Attachment (PATA)</strong> - Parallel ATA (PATA), originally named AT Attachment, is a standard interface for attaching storage devices in computers such as disk drives, floppy disk drives, and optical disks.</li>
<li><strong>Front-side Bus (FSB)</strong> - A front-side bus (FSB) is a network networking bus that was mostly in computers built on Intel-chips. It carries data between the CPU and memory controller hub known as northbridge.</li>
<li><strong>IEEE 1284</strong> - is a standard which specifies simultaneous I/O parallel communication between computers and other devices. It was initially established by Centronics in the 1970s and became commonly recognized as the Centronics terminal, both before and after its standardization with IEEE.</li>
<li><strong>Small Computer System Interface (SCSI)</strong> - is more widely used with hard disk drives and cassette drives although it can connect a large range of other items, including scanners and CD players, but not all controllers can accommodate these items.</li>
</ol>

Coursework 2

Five Steps of Good System Design Project Proposal

<h4>Realtime Electrocardiogram (ECG) Monitoring System</h4>
<br />
<h5>Front Panel:</h6>
<img src="https://i.imgur.com/uL72Z48.png" class="img-fluid" alt=''front panel" />
<br /><br />
<h5>Block Diagram:</h6>
<img src="https://i.imgur.com/LQ8RkSm.png"class="img-fluid" alt="block diagram"/>
<br /><br />

<p>Word File: <a href="https://drive.google.com/file/d/1pbX2TdxABHplJNvstmLxas0XRbQ93gcl/view?usp=sharing" target="_blank">Download Here</a></p>
<p>Powerpoint File: <a href="https://drive.google.com/file/d/1FJ2VYYBXfZCUqV2V4lxrjezE5joXg8Tk/view?usp=sharing" target="_blank">Download Here</a></p>
<p>LabView .vi File: <a href="https://drive.google.com/file/d/19qyJ4ITFf1Pm0WhDlCfZFUApSW2iEAV9/view?usp=sharing" target="_blank">Download Here</a></p>

Coursework 2 - Seatwork

<h5>Read 5 IEEE papers related to embedded systems. Summarize the 5 articles by describing the problem the paper solve, methodology they used and the results.</h5><br />
<p>Word File: <a href="https://drive.google.com/file/d/1MNbE7cbN8po6QFRi320faBDIzgsGO5nC/view?usp=sharing" target="_blank">Download Here</a></p>

Coursework 3

<h5>Click the download link</h5>
<p>Word file: <a href="https://drive.google.com/file/d/1fV9pgLOszTCJLCQO8A_ps2qjkGSy_ECl/view?usp=sharing" target="_blank">Click here to download</a></p>

CPE109L

<h5>This experiment contains two parts.</h5>
<p>Word file: <a href="https://drive.google.com/file/d/1rQ96z7YTwxGcCDdr4tAWcE-OGuO1L1MU/view?usp=sharing" target="_blank">Click here to download</a><br>
Analyze.vi File: <a href="https://drive.google.com/file/d/12--a-oDTou_geuzV6mlyIn974_d329sf/view?usp=sharing" target="_blank">Click here to download</a></p>

Explore the Functionality of While Loop I/O Tunnels

<h5>This experiment contains two parts. Input and Output Tunnels.</h5>

<p>Word file: <a href="https://drive.google.com/file/d/1-ydd3dxVPe9GH12y-mJ7aSgMK9rB3Ag9/view?usp=sharing" target="_blank">Click here to download</a><br>
LabView .vi File: <a href="https://drive.google.com/file/d/1RND9Nb7rnbBOOyndAGl6iWB1LvEIR27S/view?usp=sharing" target="_blank">Click here to download</a></p>

Laboratory Experiment 3

<h5>Click the download links below</h5>

<p>Word file: <a href="https://drive.google.com/file/d/1Dh3m1G3XXgJz1yTQmsy9lIYDJIEC-GEx/view?usp=sharing" target="_blank">Click here to download</a><br>
LabView .vi File: <a href="https://drive.google.com/file/d/1rLfwUevJ8SB-pojAFP0JTR0NuqL7ZGLl/view?usp=sharing" target="_blank">Click here to download</a></p>

Laboratory Experiment 5

Familiarization of Express PCB Schematic and Layout

<h5>Audio Oscillator</h5>
<img src="https://i.imgur.com/ig8zMnM.png" alt="Experiment 1 CPE113L" class="img-fluid" /><br><br>
<p>Questions, Results and Discussion, Conclusion:  <a href="https://drive.google.com/file/d/1GCT0evTDFWosa3GMNbFV-uhw9gGCnDhJ/view?usp=sharing" target="_blank">Click here to download</a><br>
PCB File:  <a href="https://drive.google.com/file/d/1NMDiOT2nT5rRDIAoFAhiHLRreUTrvJti/view?usp=sharing" target="_blank">Click here to download</a><br>
Schematic File:  <a href="https://drive.google.com/file/d/1bPxKGOF6sfeq4OlzYKUShoFjfVEW0HHJ/view?usp=sharing" target="_blank">Click here to download</a></p>

CPE113L

<h5>Ultrasonic Insect Repellent</h5>
<img src="https://i.imgur.com/nfJwySR.jpg" alt="Experiment 2 CPE113L" class="img-fluid" /><br><br>
<p>Questions, Results and Discussion, Conclusion:  <a href="https://drive.google.com/file/d/175NHb13-nUKtBemEhq3Llgu7xc1YLfby/view?usp=sharing" target="_blank">Click here to download</a><br>
PCB File:  <a href="https://drive.google.com/file/d/1ifN9ojCtY0-79R5VOOYd09ICQHbcf5F_/view?usp=sharing" target="_blank">Click here to download</a><br>
Schematic File:  <a href="https://drive.google.com/file/d/1h4SFXuIGxQ6MbQ0hoXzb1QpvuZl-LMAs/view?usp=sharing" target="_blank">Click here to download</a></p>

<h5>Selective Timer Alarm</h5>
<img src="https://i.imgur.com/daKK2Ko.jpg" alt="Experiment 2 CPE113L" class="img-fluid" /><br><br>
<p>Questions, Results and Discussion, Conclusion:  <a href="https://drive.google.com/file/d/1OhpruW33wY3mSb9bjg7C0cNqthUkmOit/view?usp=sharing" target="_blank">Click here to download</a><br>
PCB File:  <a href="https://drive.google.com/file/d/1S_1d2V96FHCYLRj9C4Sh1YvELzamePdf/view?usp=sharing" target="_blank">Click here to download</a><br>
Schematic File:  <a href="https://drive.google.com/file/d/16xjnPIhJcY5bD2KruB9jSJbvUijRBYlS/view?usp=sharing" target="_blank">Click here to download</a></p>

<h5>Digital Dice</h5>
<img src="https://i.imgur.com/mxycfr0.jpg" alt="Experiment 2 CPE113L" class="img-fluid" /><br><br>
<p>Questions, Results and Discussion, Conclusion:  <a href="https://drive.google.com/file/d/1nDcrJylsfuFe4REveY4ZFoEfZuZ7_tw3/view?usp=sharing" target="_blank">Click here to download</a><br>
PCB File:  <a href="https://drive.google.com/file/d/1en8OOsE85zXfCG6umnRllL9GJR2pyxCN/view?usp=sharing" target="_blank">Click here to download</a><br>
Schematic File:  <a href="https://drive.google.com/file/d/12_F3d3q0nRzqpTlqqvOL9tSBe3TdCrnE/view?usp=sharing" target="_blank">Click here to download</a></p>

Laboratory Experiment 4

<h5>Electronic Game</h5>
<img src="https://i.imgur.com/DJe5PXP.jpg" alt="Experiment 2 CPE113L" class="img-fluid" /><br><br>
<p>Questions, Results and Discussion, Conclusion:  <a href="https://drive.google.com/file/d/1v8e04t3Xy3e-l_pTpjVgvGq2TAKrXa1H/view?usp=sharing" target="_blank">Click here to download</a><br>
PCB File:  <a href="https://drive.google.com/file/d/1VBf5nwB4MXtL5njTJuQPeiMQPJGK0wS0/view?usp=sharing" target="_blank">Click here to download</a><br>
Schematic File:  <a href="https://drive.google.com/file/d/1BxmXQuWT43NGmgOJ8EAr-5WOH82r6BLy/view?usp=sharing" target="_blank">Click here to download</a></p>

<h5>Voice Modulator</h5>
<img src="https://i.imgur.com/twMp9kT.png" alt="Experiment 2 CPE113L" class="img-fluid" /><br><br>
<p>Questions, Results and Discussion, Conclusion:  <a href="https://drive.google.com/file/d/1Bd9SN0AprG2ImwBJzmweg0rm--mvs7dW/view?usp=sharing" target="_blank">Click here to download</a><br>
PCB File:  <a href="https://drive.google.com/file/d/1-v5QHrNT3Vzlh_MjJFsNPq-ZFoQf-UIY/view?usp=sharing" target="_blank">Click here to download</a><br>
Schematic File:  <a href="https://drive.google.com/file/d/1kHBeCX-KwMjYX2WkhhqVosZy2c2KF9cd/view?usp=sharing" target="_blank">Click here to download</a></p>

Laboratory Experiment 6

<h5>Fire Alarm System</h5>
<hr>
<h5>Schematic</h5>
<img src="https://i.imgur.com/ocroomU.jpg" alt="DOE CPE113L" class="img-fluid" />
<p>SCH File:  <a href="https://drive.google.com/file/d/1aLKHq-s4xGonONdTW0XUEeBgxU5EDqtX/view?usp=sharing" target="_blank">Click here to download</a></p><hr>

<h5>PCB</h5>
<img src="https://i.imgur.com/Ur3KOUb.png" alt="DOE CPE113L" class="img-fluid" />
<p>PCB File:  <a href="https://drive.google.com/file/d/1kGTJBGTS8KbvEAvGnXAq_EKYL7QHf8Mj/view?usp=sharing" target="_blank">Click here to download</a></p><hr>

<h5>Laboratory Procedures</h5>
<p>PDF File:  <a href="https://drive.google.com/file/d/1yRvJZDdTbMHIm9zBA5b4nyCMt51kdUjQ/view?usp=sharing" target="_blank">Click here to download</a></p>

The Emergence of the Global Village through the Globalization of Media

<h5>Click on the title of the article to download a file.</h5><br />
<p>Extended Essay: <a href="https://drive.google.com/file/d/1Jsq1ggH01d_3_Lcul_ssgWOJJTxtQVkf/view?usp=sharing" target="_blank">The Emergence of the Global Village through the Globalization of Media </a></p>

GED105

Extended Essay

<h5>Click on the title of the article to download a file.</h5><br />
<a href="https://drive.google.com/file/d/18e6Po-9DsDkMXdywhFeLVROdXsbFBx_s/view?usp=sharing" target="_blank">Her: Reaction Paper</a>

CPE101

Reaction Paper

Matlab coding of topics from CO2 to CO4 Set 2

<h5>Course Outcome 2</h5>
<li>Integration of exponential function</li>
<pre class="line-numbers"><code class="lang-matlab">syms x
int(1/(5+2*exp(x)))</code></pre>
<br />
<li>Integration by trigonometric transformation</li>
<pre class="line-numbers"><code class="lang-matlab">syms x
int((csc(x)^8)*(cot(x)^2))</code></pre>
<br />
<li>Integration by trigonometric substitution</li>
<pre class="line-numbers"><code class="lang-matlab">syms x
int((exp(x))*(sqrt(9-exp(2*x))))</code></pre>
<br /><br /><br />


<h5>Course Outcome 3</h5>
<li>Definite Integral</li>
<pre class="line-numbers"><code class="lang-matlab">syms x
int(((x^2 + 2*x + 3)/(x^3+3*x^2+3*x)),1, 5)</code></pre>
<br />
<li>Definite integrals of absolute value functions</li>
<pre class="line-numbers"><code class="lang-matlab">syms x
int(abs(x^2 + 6*x + 8),-8,4)

f(x)=abs(x^2 + 6*x + 8);
fplot(abs(x^2 + 6*x + 8),[-10,6])
daspect([1 8 1]);
grid on
%line([-1,-1],[0,0]);
line([7,7],[-5,0]);</code></pre>
<br />
<li>Area of a plane region</li>
<pre class="line-numbers"><code class="lang-matlab">syms x
int((3-sqrt(x)),0,9)

y = @(x) (3-sqrt(x));
x = linspace(0, 9);
inty = cumtrapz(x,y(x));
figure(1)
plot(x, inty, '-k', 'LineWidth',1)
hold on
patch([x fliplr(x)], [zeros(size(x)) fliplr(inty)], 'g')
hold off
grid</code></pre>
<br /><br /><br />

<h5>Course Outcome 4</h5>
<li>Double Integrals</li>
<pre class="line-numbers"><code class="lang-matlab">syms x y
int(int(sqrt(x+y),x,0,3*y),y,0,1)</code></pre>
<br />
<li>Triple integrals</li>
<pre class="line-numbers"><code class="lang-matlab">syms x y z
int(int(int(x*y*z,z,1,y),y,-1,x^2),x,0,2)</code></pre>
<br />
<li>Double integrals over nonrectangular regions</li>
<pre class="line-numbers"><code class="lang-matlab">syms x y
int(int(x,y,exp(x),exp(2)),x,0,2)

round(int(int(x,y,exp(x),exp(2)),x,0,2)) %Rounded answer

clear all, close all; clc
x = 0 : 2;
curve1 = exp(x);
curve2 = exp(2)+0*x;
plot(x, curve2, 'b', 'LineWidth', 1);
hold on;
plot(x, curve1, 'b', 'LineWidth', 1);
x2 = [x, fliplr(x)];
inBetween = [curve1, fliplr(curve2)];
fill(x2, inBetween, 'g');
grid</code></pre>

Project Set 2

Realtime Electrocardiogram (ECG) Monitoring System

Metacognitive Reading Report 1 - Ideologies of globalization

<p>MRR 1: <a href="https://drive.google.com/file/d/1vlVS7UTG-rU_DPgPCcB35khb-TTUJYVC/view?usp=sharing" target="_blank">Ideologies of globalization </a></p>

MRR1

Metacognitive Reading Report 2 - Definitions of Globalization: A Comprehensive Overview and a Proposed Definition

<p>MRR 2: <a href="https://drive.google.com/file/d/1ULgllJ6vIBOjr7YwoI0Nnhv5aQpYMg9Z/view?usp=sharing" target="_blank">Definitions of Globalization: A Comprehensive Overview and a Proposed Definition</a></p>

MRR2

Metacognitive Reading Report 3 - Integration Processes In The Global Economy: Current State and Prospects. The Cases of The European Union, ASEAN Economic Community, And NAFTA

<p>MRR 3: <a href="https://drive.google.com/file/d/1KOFsYEqfJzC6hnolwE6zFTIs2S17H4yj/view?usp=sharing" target="_blank">Integration Processes In The Global Economy: Current State and Prospects. The Cases of The European Union, ASEAN Economic Community, And NAFTA</a></p>

MRR3

Metacognitive Reading Report 4 - Globalization from Below: The Rise of Transnational Communities

<p>MRR 4: <a href="https://drive.google.com/file/d/188t7TPORlwMlJgYAajSSp_eNgs8twA5G/view?usp=sharing" target="_blank">Globalization from Below: The Rise of Transnational Communities</a></p>

MRR4

Metacognitive Reading Report 6 - Crossing Borders: development, learning and the North – South divide

<p>MRR 6: <a href="https://drive.google.com/file/d/1Gpzw-ZPUsv4J2Y9zJ54UVdbkygNR3Rdr/view?usp=sharing" target="_blank">Crossing Borders: development, learning and the North – South divide</a></p>

MRR6

Metacognitive Reading Report 7 - The Rise of New Urban Middle Classes in Southeast Asia: What is its national and regional significance?

<p>MRR 7: <a href="https://drive.google.com/file/d/170Udwgle0AOBErFZE_3_-9mlRc2_-uJd/view?usp=sharing" target="_blank">The Rise of New Urban Middle Classes in Southeast Asia: What is its national and regional significance?</a></p>

MRR7

Metacognitive Reading Report 8 - Globalization of Culture Trough the Media

<p>MRR 8: <a href="https://drive.google.com/file/d/18Gb5t1vUGNAlC_egTfh6gqgAALLURxfg/view?usp=sharing" target="_blank">Globalization of Culture Trough the Media</a></p>

MRR8

Metacognitive Reading Report 9 - Religious Dimensions of Political Conflict and Violence

<p>MRR 9: <a href="https://drive.google.com/file/d/1HmTpf3JlDs_A8bj6jcZzb302QwSKjgnK/view?usp=sharing" target="_blank">Religious Dimensions of Political Conflict and Violence</a></p>

MRR9

Metacognitive Reading Report 10 - The Global City: Introducing a Concept

<p>MRR 10: <a href="https://drive.google.com/file/d/1Rds7mUFY5q773nZSJh36zPNejCxT-oTZ/view?usp=sharing" target="_blank">The Global City: Introducing a Concept</a></p>

MRR10

Metacognitive Reading Report 11 - Overview: 2016 Syria Humanitarian Response Plan & 2016-2017 Regional Refugee and Resilience Plan

<p>MRR 11: <a href="https://drive.google.com/file/d/12_bEnSNJyPDST7Rmkmza7f1UtMCy_T1u/view?usp=sharing" target="_blank">Overview: 2016 Syria Humanitarian Response Plan & 2016-2017 Regional Refugee and Resilience Plan</a></p>

MRR11

Metacognitive Reading Report 12 - A Development Approach to Migration and Displacement

<p>MRR 12: <a href="https://drive.google.com/file/d/1dW41cT8J_IcAZjW-YK1zJ0rHy9pKwJFm/view?usp=sharing" target="_blank">A Development Approach to Migration and Displacement</a></p>

Introduction to HDL (Hardware Design Language)