Drill5_1

module flip_flop (clk, reset, d, q); input clk, reset, d; output q; 
reg q; 
 
always @ (posedge clk ) begin 
if (reset == 1)  begin q <= 0; 
end 
else  begin q <= d; 
end 
end 
endmodule 
module circuit_ff(input clk, reset, x, output y); 
 	wire OR1, OR2, AND1, AND2, AND3;  	wire A, B, Bnot; 
 	not (Bnot, B); 
 	flip_flop ff1(clk, reset, OR1, A);  	flip_flop ff2(clk, reset, OR2, B); 
 	and (AND1,A,x), (AND2,B,x), (AND3,Bnot,x), (AND4,A,B); 
 	or (OR1, AND1,AND2), (OR2,AND1,AND3);  	and (y,B,A); 
endmodule 
 
module drill5_1; 
 	reg clk, reset,d;  	wire q; 
 	circuit_ff cff(clk, reset, d, q); 
 	 	 
 	initial begin 
 	 	 	clk=0; reset=1; d=0; 
 	 	 	$monitor("clk=%b reset=%b d=%b q=%b",clk,reset,d,q); 
 	end 
 	initial begin  	 	forever #1 clk=~clk; 
 	end 
 	initial fork 
 	 	#1 reset=0; 
 	 	#2 d=1; 
 	 	#3 reset=1; 
 	 	#4 reset=0; 
 	 	#5 d=0; 
 	 	#8 d=1; 
 	 	#10 $finish;  	join 
endmodule

Drill5_2

module mux_8_1 (output reg m_out, input [7:0]in_x, input[2:0] select); 
 	always@(in_x[0],in_x[1],in_x[2],in_x[3],in_x[4],in_x[5],in_x[6],in_x[7],select
) 
 	case(select) 
 	3'b000: m_out=in_x[0];  
 	3'b001: m_out=in_x[1]; 
 	3'b010: m_out=in_x[2]; 
 	3'b011: m_out=in_x[3]; 
 	3'b100: m_out=in_x[4]; 
 	3'b101: m_out=in_x[5]; 
 	3'b110: m_out=in_x[6]; 
 	3'b111: m_out=in_x[7];  	endcase 
endmodule 
 
module drill5_2();  	reg [7:0] x;  	reg [2:0] select; 
 	wire m_out; 
 	 
 mux_8_1 MUX1(m_out, x, select);  initial begin 
 	  	select=2'b00; x=8'h4F;  	 	$strobe("Select Input Output"); 
 	 	$monitorb(select,"    ", x, "   ", m_out); 
 	 	#1 select=3'b000; 
 	 	#1 select=3'b001; 
 	 	#1 select=3'b010; 
 	 	#1 select=3'b011; 
 	 	#1 select=3'b100; 
 	 	#1 select=3'b101; 
 	 	#1 select=3'b110; 
 	 	#1 select=3'b111; 
	 	#1 $display("Changing value of input"); 
 	 	#1 x=8'h98; 
 	 	#1 select=3'b000; 
 	 	#1 select=3'b001; 
 	 	#1 select=3'b010; 
 	 	#1 select=3'b011; 
 	 	#1 select=3'b100; 
 	 	#1 select=3'b101; 
 	 	#1 select=3'b110; 
 	 	#1 select=3'b111;  	 
 	 	#100 $finish;  	
end 
endmodule

Drill5_3

module state_diagram(  	output reg y_out,   	input x_in, clock, reset ); 
 
 	reg[1:0] state, next_state;  	parameter S0=2'b00, 
 	 	  S1=2'b01, 
 	 	  S2=2'b10,  	 	  S3=2'b11; 
 	always@(posedge clock, negedge reset)  	 	if (reset==0) state <= S0;  	 	else state <= next_state; 
 	always@(state, x_in)  	 	case (state) 
 	 	S0: 	if (x_in) next_state=S1; else next_state=S0; 
 	 	S1: 	if (x_in) next_state=S3; else next_state=S0; 
 	 	S2: 	if (~x_in) next_state=S0; else next_state=S2;  	 	S3: 	if (x_in) next_state=S2; else next_state=S0; 
 	 	endcase 
 	always@(state, x_in)  	 	case (state) 
 	 	S0: 	 	y_out=0; 
 	 	S1,S2,S3: 	y_out=~x_in; 
 	 	endcase 
endmodule 
 
module drill5_3; 
 	wire t_y_out; 
 	reg t_x_in, t_clock, t_reset; 
 	state_diagram 	sd(t_y_out, t_x_in, t_clock, t_reset);  	initial #200 $finish;  	initial begin  
 	 	t_clock=0; 
 	 	forever #5 t_clock=~t_clock; 
 	 
 	end 
 	initial fork 
 $monitor($time,,"reset=%b clock=%b x=%b y=%b" ,t_reset, t_clock, t_x_in, t_y_out); 
 	 	t_reset=0; 
 	#2 	t_reset=1; 
 	#87 	t_reset=0; 
 	#89 	t_reset=1; 
 	#10 	t_x_in=1; 
 	#30 	t_x_in=0; 
 	#40 	t_x_in=1; 
 	#50 	t_x_in=0; 
 	#52 	t_x_in=1; 
 	#54 	t_x_in=0; 
 	#70 	t_x_in=1; 
 	#80 	t_x_in=1; 
 	#70 	t_x_in=0; 
 	#90 	t_x_in=1; 
 	#100 t_x_in=0; 
 	#120 t_x_in=1; 
 	#160 t_x_in=0; 
 	#170 t_x_in=1;  	join 
endmodule

Exercise5_1

module t_flip_flop(clk, reset, t_in, t_out);
	input clk, reset, t_in;
	output t_out;
	reg t_out;

	always @ (negedge clk)
	begin
		if(reset == 1)
		begin
			t_out <= 0;
		end
		else if (t_in == 1)
		begin
			t_out <= ~t_out;
		end
		else
		begin
			t_out <= t_out;
		end
	end
endmodule

module circuit_tff(input clk, reset, x, output [2:0]t_out);
	wire clk1, clk2;
	t_flip_flop tff0(clk, reset, x, clk1);
	buf bf1(t_out[0], clk1);
	t_flip_flop tff1(clk1, reset, x, clk2);
	buf bf2(t_out[1], clk2);
	t_flip_flop tff2(clk2, reset, x, t_out[2]);

endmodule

module exercise5_1;
	reg clk, rst, t_in;
	wire [2:0] t_out;
	circuit_tff ctff(clk, rst, t_in, t_out);

	initial begin
		clk=0; rst=1; t_in=0;
		$monitor("clk = %b rst = %b ctr_state = %b%b", clk, rst, t_out, clk);
	end
	initial begin
		forever #1 clk = ~clk;
	end
	initial fork
		#1 rst = 0;
		#2 t_in = 1;
		#16 $finish;
	join
endmodule

Exercise5_2

module JKFF(input clk, reset,J,K, output reg Q);
 	initial Q=0;
 	always @(posedge clk)
 	begin
 		if(reset ==1)
 		begin
 			Q<=0;
 		end	
 		else
 		begin
 			if(J==0&&K==0)
 			Q<=Q;
 			else
 			begin
 				if(J==1&&K==0)
 				Q<=1;
 				else
 					begin
 					if(J==1&&K==1)
 					Q<=~Q;
 					end
 				end
 			end
 		end
endmodule

module circuit(input clk, reset, X, Y, output F1, F2);
	//input clk, reset, X, Y;
	//output F1,F2;
	wire Xnot;
	wire [3:0] eor;
	wire J1, J2, K1, K2;
	wire A, B;

	not M1(Xnot,X);
	xor M2(eor[3],Y,F2), M3(eor[0],Y,F1);
	xnor M4(eor[2],Y,F2), M5(eor[1],Y,F1);
	and M6(J1,Xnot,eor[3]), M7(K1,Xnot, eor[2]), M8(J2,Xnot,eor[1]), M9(K2,Xnot,eor[0]);

	JKFF jkff1(clk, reset, J1,K1,A);
	JKFF jkff2(clk, reset, J2,K2,B);

	buf(F1,A);
	buf(F2,B);
	endmodule

module exercise5_2;
	reg clk, reset, J,K,A,B;
	wire F1, F2;
	circuit ckt1(clk, reset, A,B,F1,F2);

	initial
	begin
	clk=0; reset =0;
	$display("\t           T CLK  A B F1 F2");
	end

	initial begin
	$monitor ($time,,,"%b   %b %b %b  %b ",clk,A,B,F1,F2);
	end

	always #1 clk=!clk;

	initial begin
	A = 1'b0; B = 1'b0;
	#8 A = 1'b0; B = 1'b1;
	#8 A = 1'b1; B = 1'b0;
	#8 A = 1'b1; B = 1'b1;
	#8 $finish;
	end
endmodule

Exercise5_3

module flip_flop(clk,reset,d,q);
	input clk, reset,d;
	output q;
	reg q;
	initial begin
	q=0;
end
	always@(posedge clk)
	begin
	if(reset==1)
	begin
	q<=0;
	end
	else
	begin
	q<=d;
	end
	end
endmodule

module mux_4_1(output reg m_out, input IN0,IN1, IN2, IN3, input[1:0] select);
	always@(IN0, IN1, IN2, IN3, select)
	case(select)
	2'b00:m_out=IN0;
	2'b01:m_out=IN1;
	2'b10:m_out=IN2;
	2'b11:m_out=IN3;
	endcase
endmodule

module circuit_ff(input clk, reset, input[3:0] U, input[1:0] sel, output T3, T2,T1,T0);
	wire A,B,C,D,O1,O2,O3,O4, zero1;
	buf (zero1,0);
	flip_flop ff1(clk,reset,O1,A);
	flip_flop ff2(clk,reset,O2,B);
	flip_flop ff3(clk,reset,O3,C);
	flip_flop ff4(clk,reset,O4,D);

	mux_4_1 mux1(O1,A,B,U[3],B,sel);
	mux_4_1 mux2(O2,B,C,U[2],C,sel);
	mux_4_1 mux3(O3,C,D,U[1],D,sel);
	mux_4_1 mux4(O4,D,zero1,U[0],zero1,sel);

	buf(T3,A);
	buf(T2,B);
	buf(T1,C);
	buf(T0,D);
endmodule

module exercise5_3();
	reg clk,reset;
	reg[3:0] U;
	reg[1:0] select;
	wire OUT3, OUT2,OUT1,OUT0;

	circuit_ff circ(clk, reset, U, select, OUT0, OUT1,OUT2,OUT3);
	initial begin
	select=2'b00;
	U=8'hAF;
	reset=0;
	clk=0;
	$strobe("clk  sel    in     out");
	$monitorb(clk, "    ", select, "    ", U, "    ", OUT0, OUT1,OUT2,OUT3);
	#1 select=2'b01;
	#1 select=2'b01;
	#1 select=2'b10;
	#1 select=2'b10;
	#1 select=2'b11;
	#1 select=2'b11;
	#1 select=2'b00;
	#1 select=2'b01;
	#1 select=2'b10;
	#1 select=2'b01;
	#1 select=2'b10;
	#1 select=2'b11;
	#10 $finish;
	end
	initial begin
	forever #1 clk=~clk;
	end
endmodule

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