Drill1_1

//Verilog model of circuit of Fig 1.1
module circuit1_1(A, B, C, X);

	input A, B, C;
	output X;
	wire wire1, wire2, wire3;

	not NOT(wire2, A);
	xor EOR2(wire1, B, C);
	and AND2(wire3, wire1, A);
	nor NOR2(X, wire3, wire2);

endmodule




//Test bench for the Verilog model of Fig 1.1
module testbench1_1;

	reg A, B, C;
	wire Z;
	circuit1_1 tb1(A, B, C, Z);
	initial
	begin
		A=1'b0; B=1'b0; C=1'b0;
		$display("Simulating output for circuit1_1");
		$monitor($time,,,"A=%b B=%b C=%b Z=%b",A,B,C,Z);

		#2 A=1'b0; B=1'b0; C=1'b1;
		#1 A=1'b0; B=1'b1; C=1'b0;
		#1 A=1'b0; B=1'b1; C=1'b1;
		#1 A=1'b1; B=1'b0; C=1'b0;
		#1 A=1'b1; B=1'b0; C=1'b1;
		#1 A=1'b1; B=1'b1; C=1'b0;
		#1 A=1'b1; B=1'b1; C=1'b1;
		#2 $finish;
	end
endmodule

Drill1_2

//behavioural Verilog code for a simple 1-bit full subtracter.
module full_subtract(diff, borrowOut, a, b, borrowIn);
	output diff;
	output borrowOut;
	input a, b, borrowIn;
	assign {borrowOut, diff}=a-b-borrowIn;
	//result of subtraction is two bits; the MSB is borrowOut and the LSB
	//is diff.
endmodule

module testingFS();

	reg a, b,borrowIn;
	wire diff, borrowOut;
	full_subtract fs(diff, borrowOut, a, b, borrowIn);

	initial begin
	a=1'b1; b=1'b1; borrowIn=1'b0;
	end

	initial begin
	#10 a=1'b1;
	#10 a=1'b0; b=1'b1;
	#10 a=1'b1; b=1'b0;
	#10 borrowIn=1'b1;
	end

	initial begin
	$display(" a b borrowIn difference borrowOut time");
	$monitor(" %b %b %b %b %b %b ", a, b, borrowIn, diff,
		borrowOut, $time);
	#10 $finish;
	end
endmodule

Exercise 1_1

module exercise1_1(W, X, Y, Z);

	output [0:3] W;
	input X, Y;
	input Z;
	wire X1, Y1, Z1;

	not G1(X1, X), G2(Y1, Y),G3(Z1, Z);

	nand G4(W[0], X1, Y1, Z1),G5(W[1], X1, Y, Z1),
		G6(W[2], X, Y1, Z1),G7(W[3], X, Y, Z1);
endmodule


module testbenchEx1_1;
	reg X, Y, Z;
	wire [0:3] O;
	exercise1_1 tb1_2(O, X, Y, Z);
	initial
	begin
		X=1'b0; Y=1'b0; Z=1'b0;
		$display("Simulating output for exercise1_1");
		$monitor($time,,,"X=%b Y=%b Z=%b O=%b", X, Y, Z, O);

		#0 X=1'b0; Y=1'b0; Z=1'b0;
		#1 X=1'b0; Y=1'b0; Z=1'b1;
		#1 X=1'b0; Y=1'b1; Z=1'b0;
		#1 X=1'b0; Y=1'b1; Z=1'b1;
		#1 X=1'b1; Y=1'b0; Z=1'b0;
		#1 X=1'b1; Y=1'b0; Z=1'b1;
		#1 X=1'b1; Y=1'b1; Z=1'b0;
		#1 X=1'b1; Y=1'b1; Z=1'b1;
		#2 $finish;
	end
endmodule

Exercise1_2

//Verilog model of circuit of Fig 1.1
module circuit1_1(A, B, C, X);	

	input 		A, B, C;
	output	X;
	wire		wire1, wire2, wire3;
	
	not		NOT(wire2, A);
	xor		EOR2(wire1, B, C);
	and		AND2(wire3, wire1, A);
	nor		NOR2(X, wire3, wire2);

endmodule

//Test bench for the Verilog model of Fig 1.1
module  testbench1_1;
	
	reg		A, B, C;
	wire		Z;
	circuit1_1	tb1(A, B, C, Z);
	initial
	begin
		$display("Simulating output for exercise1_2");

		#1 A=1'b0; B=1'b0; C=1'b0;
		$display($time,,,"A=%b B=%b C=%b Z=0",A,B,C);
		#1 A=1'b0; B=1'b0; C=1'b1;
		$display($time,,,"A=%b B=%b C=%b Z=%b",A,B,C,Z);
		#1 A=1'b0; B=1'b1; C=1'b0;
		$display($time,,,"A=%b B=%b C=%b Z=%b",A,B,C,Z);
		#1 A=1'b0; B=1'b1; C=1'b1;
		$display($time,,,"A=%b B=%b C=%b Z=%b",A,B,C,Z);
		#1 A=1'b1; B=1'b0; C=1'b0;
		$display($time,,,"A=%b B=%b C=%b Z=%b",A,B,C,Z);
		#1 A=1'b1; B=1'b0; C=1'b1;
		$display($time,,,"A=%b B=%b C=%b Z=1",A,B,C);
		#1 A=1'b1; B=1'b1; C=1'b0;
		$display($time,,,"A=%b B=%b C=%b Z=0",A,B,C);
		#1 A=1'b1; B=1'b1; C=1'b1;
		$display($time,,,"A=%b B=%b C=%b Z=0",A,B,C);

		#2 $finish;
	end
endmodule

Exercise1_3

module exercise1_3(
	output	 var1, x_4,
	input 		x_1, x_2, x_3);
	xor		EOR1(x_4, x_1, x_2, x_3);
	xor		EOR2(var1, x_1, x_2, x_3, x_4);
endmodule

//testbench
module testbench1_3;
	reg x_1,x_2,x_3;
	wire var1,x_4;
	exercise1_3 tb1(var1,x_4,x_1,x_2,x_3);
	initial
	begin
		x_1=1'b0; x_2=1'b0; x_3=1'b0;
		$display("Simulating output for Exercise1_3");
		$monitor($time,,,"x_1=%b x_2=%b x_3=%b var1=%b x_4=%b",x_1,x_2,x_3,var1,x_4);

		#1 x_1=1'b0;x_2=1'b0;x_3=1'b1;
		#1 x_1=1'b0;x_2=1'b1;x_3=1'b0;
		#1 x_1=1'b0;x_2=1'b1;x_3=1'b1;
		#1 x_1=1'b1;x_2=1'b0;x_3=1'b0;
		#1 x_1=1'b1;x_2=1'b0;x_3=1'b1;
		#1 x_1=1'b1;x_2=1'b1;x_3=1'b0;
		#1 x_1=1'b1;x_2=1'b1;x_3=1'b1;
		#2 $finish;
	end
endmodule

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