Drill6_1

module magcom (input [3:0] A, B, output lt, gt, eq);
	assign lt=(A<B);
	assign gt=(A>B);
	assign eq=(A==B);
endmodule

module drill6_1;
	reg [3:0] A, B;
	wire lt, gt, eq;
	magcom tb(A, B, lt, gt, eq);
	reg [255:0]string1, string2, string3;
	
	initial fork
		A=1'b0; B=1'b0;
		$display(" A B \t\t\t\t A<B \t\t \t\t A>B\t\t\t\t A==B");
		$monitor("%d %d %s %s %s",A, B, string1, string2, string3);
	join
	initial begin
		#1 A=4'd7;
		B=4'd7;
		if (lt==1) string1="true";
		else string1="false";
		if (gt==1) string2="true";
		else string2="false";
		if (eq==1) string3="true";
		else string3="false";
		#3 A=4'd4;
		B=4'd6;
		if (lt==1) string1="true";
		else string1="false";
		if (gt==1) string2="true";
		else string2="false";
		if (eq==1) string3="true";
		else string3="false";
		#5 A=4'd9;
		B=4'd8;
		if (lt==1) string1="true";
		else string1="false";
		if (gt==1) string2="true";
		else string2="false";
		if (eq==1) string3="true";
		else string3="false";
		#7 A=4'd10;
		B=4'd1;
		if (lt==1) string1="true";
		else string1="false";
		if (gt==1) string2="true";
		else string2="false";
		if (eq==1) string3="true";
		else string3="false";
		#9 $finish;
	end
endmodule

Drill6_2

module AllBit(input [31:0]x, output zero, one);
	assign zero=~(|x);
	assign one=&x;
endmodule

module drill6_2;
	reg [31:0] inputX;
	wire outputZ, outputO;
	
	AllBit Abit(inputX, outputZ, outputO);
	initial fork
		$monitor($time,,," %h",inputX," %h",outputO," %h",outputZ);
		inputX=32'h0;
		#1 inputX=32'h12345678;
		#2 inputX=0;
		#3 inputX=32'hFFFFFFFF;
		#4 inputX=32;
		#4 $finish;
	join
endmodule

Drill6_3

module JK_flipflop(output A, input J, K, clk, reset);
	wire AofJK;
	assign AofJK=(J&~A)|(~K&A);
	D_flipflop JKf(A,AofJK,clk, reset);
endmodule

module D_flipflop(output reg B, input D, clk, reset);
	always@(posedge clk, negedge reset)
	begin
		if(~reset)
			B<=1'b0;
		else
			B<=D;
	end
endmodule

module drill6_3;
	reg J, K, clk, reset;
	wire Q;
	always #1 clk=~clk;
	
	JK_flipflop JKF(Q,J,K,clk,reset);
	
	initial clk=0;
	initial reset=0;
	initial J=0;
	initial K=0;
	initial $monitor("clk=%b reset=%b, J=%b, K=%b, Q=%b",clk,reset,J,K,Q);

	initial fork
		#28 $finish;
		#2 reset=1;
		#4 J=1;
		#8 K=1;
		#12 J=0;
		#16 K=0;
		#20 J=1;
		#24 J=0;
	join
endmodule

Exercise6_1

module checkCntr(disp, A, B);
	output reg [255:0] disp;
	input [7:0] A, B;
	reg [7:0] tmpA, tmpB;
	integer Acnt, Bcnt;
	wire gthan, lthan, eqls;

	always @(A, B) begin
		Acnt=0; Bcnt=0;
		tmpA=A; tmpB=B;
		repeat (8) begin
			Acnt = Acnt + tmpA[0];
			Bcnt = Bcnt + tmpB[0];
			tmpA = tmpA >> 1;
			tmpB = tmpB >> 1;
		end
		if(gthan) disp=">";
		else if(lthan) disp="<";
		else disp="=";
	end

	assign gthan = (Acnt > Bcnt);
	assign lthan = (Acnt < Bcnt);
	assign eqls = (Acnt == Bcnt);
endmodule

module exercise6_1;
	reg [7:0] A, B;
	wire [255:0] disp;

	checkCntr tb(disp, A, B);

	initial begin
	A=0; B=0;
	$display("\n Comparing 8-bit input A & B\n");
	$display("\t    A         B              Comparison ");
	$monitor("\t %b  %b      %b %0s %b        ", A, B, A, disp, B);
	#2 A=8'd64; B=8'd31;
	#2 A=8'd21; B=8'd129;
	#2 A=8'd224; B=8'd7;
	#2 A=8'd2; B=8'd7;
	#2 A=8'd9; B=8'd2;
	#2 $finish;
	end
endmodule

Exercise6_2

module counter(A, B, C, clk);
	output A, B, C;
	input clk;
	reg Ta, Tb, Tc;

	T_FF Q2(A, Ta, clk, 1'h1);
	T_FF Q1(B, Tb, clk, 1'h0);
	T_FF Q0(C, Tc, clk, 1'h1);

	always @(clk) begin
		Ta=(~B&C)|(A&C)|(~A&B&~C);
		Tb=A|~B|C;
		Tc=A|~B|~C;
	end
endmodule

module T_FF(Q, Tin, clk, startVal);
	output reg Q;
	input Tin, clk, startVal;
	wire T;
	
	initial Q=startVal;

	assign T=Q^Tin;

	always @(posedge clk) begin
		Q=T;
	end
endmodule

module exercise6_2;
	wire [2:0] Q;
	reg clk;

	counter testb(Q[2], Q[1], Q[0], clk);
	
	always #2 clk=~clk;	

	initial begin
	clk=0;
	$display("\n       T flip-flop Counter");
	$display("\n    Sequence: 5-2-7-0-3-1-6-5\n");
	$display("             XYZ Val");
	$monitor("             %b  %d", Q, Q);
	#40 $finish;
	end
endmodule

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