Mapua Portfolio CPE114L

Experiment 3

Gate-Level Modeling

CPE114L

3Q1920

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Drill3_1

//Verilog model of circuit of Fig 2.1
module circuit2_1(V, W, X, Y, Z, out1);

	input V, W, X, Y, Z;
	output out1;
	wire Vnot, Wnot, Xnot, Ynot, Znot, or1, or2, or3;
	
	not U1(Vnot, V), U2(Wnot, W), U3(Xnot, X);
	not Ur(Ynot, Y), U5(Znot, Z);
	and U7(or1, Vnot, Wnot, Znot), U8(or2, W, Ynot, Z);
	and U9(or3, V, X, Z);
	or U6(out1, or1, or2, or3);

endmodule

module test2_1;
	wire w1;
	reg x1, x2, x3, x4, x5;
	
	circuit2_1 test2_1(x1, x2, x3, x4, x5, w1);
	initial begin
		x1=1'b0; x2=1'b0; x3=1'b0; x4=1'b0; x5=1'b0;
		#100 $finish;
	end
	
	initial begin
		#2 $display(x1,x2,x3,x4,x5," ",w1);
		#2 x1=1'b0; x2=1'b0; x3=1'b0; x4=1'b1; x5=1'b0; //2
		#2 $display(x1,x2,x3,x4,x5," ",w1);
		#2 x1=1'b0; x2=1'b0; x3=1'b1; x4=1'b0; x5=1'b0; //4
		#2 $display(x1,x2,x3,x4,x5," ",w1);
		#2 x1=1'b0; x2=1'b0; x3=1'b1; x4=1'b1; x5=1'b0; //6
		#2 $display(x1,x2,x3,x4,x5," ",w1);
		#2 x1=1'b0; x2=1'b1; x3=1'b0; x4=1'b0; x5=1'b1; //9
		#2 $display(x1,x2,x3,x4,x5," ",w1);
		#2 x1=1'b0; x2=1'b1; x3=1'b1; x4=1'b0; x5=1'b1; //13
		#2 $display(x1,x2,x3,x4,x5," ",w1);
		#2 x1=1'b1; x2=1'b0; x3=1'b1; x4=1'b0; x5=1'b1; //21
		#2 $display(x1,x2,x3,x4,x5," ",w1);
	end
endmodule

Drill3_2

module test2_2;
	reg [3:0]A;
	reg [1:0]sel;
	wire Out2;
	
	initial begin
		$display(" TIME A select Output");
		$monitor($time,,,,,,,"%h %d %b",A, sel, Out2);
		#50 A=4'hE; sel=2'b00;
		#50 A=4'hA; sel=2'b11;
		#50 A=4'hC; sel=2'b10;
		#50 A=4'hB; sel=2'b01;
		#50 A=4'h0; sel=2'b01;
		#50 $finish;
	end
	
	circuit2_2 t2_2(A, sel, Out2);
endmodule

module circuit2_2(input [3:0]I, input [1:0]S, output Out1);
	wire [3:0]In;
	wire S0not, S1not;
	not #(2) (S0not, S[0]);
	not #(2) (S1not, S[1]);
	and #(5) (In[0], I[0], S0not, S1not);
	and #(5) (In[1], I[1], S[0], S1not);
	and #(5) (In[2], I[2], S0not, S[1]);
	and #(5) (In[3], I[3], S[0], S[1]);
	or #(5) (Out1, In[0], In[1], In[2], In[3]);
endmodule

Exercise3_1

module exercise3_1(x, y, out1, out2, out3);
	input x, y;
	output out1, out2, out3;
	
	buf U1(out1, x);
	nand U2(out2, x, y);
	xnor U3(out3, x, y);
	
	
endmodule

module start3_1;
	wire w1, w2, w3;
	reg x1, y1;
	
	exercise3_1 start3_1(x1, y1, w1, w2, w3);
	initial begin
		x1=1'b0; y1=1'b0;
		#200 $finish;
	end
	initial begin
		#2 $display("Truth table of buf: ");
		#2 x1=1'b0;
		#2 $display("x", " ", "out");
		#2 $display(x1,"  ",w1);
		#2 x1=1'b1;
		#2 $display(x1,"  ",w1);
		#2 x1=1'bx;
		#2 $display(x1,"  ",w1);
		#2 x1=1'bz;
		#2 $display(x1,"  ",w1);
		#2 $display("");
		
		#2 $display("Truth table for nand: ");
		#2 x1=1'b0; y1=1'b0;
		#2 $display("x", " ", "y", ," ", "out");
		#2 $display(x1, " ",y1, "   ", w2);
		#2 x1=1'b0; y1=1'b1;
		#2 $display(x1, " ",y1, "   ", w2);
		#2 x1=1'b0; y1=1'bx;
		#2 $display(x1, " ",y1, "   ", w2);
		#2 x1=1'b0; y1=1'bz;
		#2 $display(x1, " ",y1, "   ", w2);
		
		#2 x1=1'b1; y1=1'b0;
		#2 $display(x1, " ",y1, "   ", w2);
		#2 x1=1'b1; y1=1'b1;
		#2 $display(x1, " ",y1, "   ", w2);
		#2 x1=1'b1; y1=1'bx;
		#2 $display(x1, " ",y1, "   ", w2);
		#2 x1=1'b1; y1=1'bz;
		#2 $display(x1, " ",y1, "   ", w2);
		
		#2 x1=1'bx; y1=1'b0;
		#2 $display(x1, " ",y1, "   ", w2);
		#2 x1=1'bx; y1=1'b1;
		#2 $display(x1, " ",y1, "   ", w2);
		#2 x1=1'bx; y1=1'bx;
		#2 $display(x1, " ",y1, "   ", w2);
		#2 x1=1'bx; y1=1'bz;
		#2 $display(x1, " ",y1, "   ", w2);
		
		#2 x1=1'bz; y1=1'b0;
		#2 $display(x1, " ",y1, "   ", w2);
		#2 x1=1'bz; y1=1'b1;
		#2 $display(x1, " ",y1, "   ", w2);
		#2 x1=1'bz; y1=1'bx;
		#2 $display(x1, " ",y1, "   ", w2);
		#2 x1=1'bz; y1=1'bz;
		#2 $display(x1, " ",y1, "   ", w2);
		#2 $display("");
		
		#2 $display("Truth table for xnor: ");
		#2 x1=1'b0; y1=1'b0;
		#2 $display("x", " ", "y", ," ", "out");
		#2 $display(x1, " ",y1, "   ", w3);
		#2 x1=1'b0; y1=1'b1;
		#2 $display(x1, " ",y1, "   ", w3);
		#2 x1=1'b0; y1=1'bx;
		#2 $display(x1, " ",y1, "   ", w3);
		#2 x1=1'b0; y1=1'bz;
		#2 $display(x1, " ",y1, "   ", w3);
		
		#2 x1=1'b1; y1=1'b0;
		#2 $display(x1, " ",y1, "   ", w3);
		#2 x1=1'b1; y1=1'b1;
		#2 $display(x1, " ",y1, "   ", w3);
		#2 x1=1'b1; y1=1'bx;
		#2 $display(x1, " ",y1, "   ", w3);
		#2 x1=1'b1; y1=1'bz;
		#2 $display(x1, " ",y1, "   ", w3);
		
		#2 x1=1'bx; y1=1'b0;
		#2 $display(x1, " ",y1, "   ", w3);
		#2 x1=1'bx; y1=1'b1;
		#2 $display(x1, " ",y1, "   ", w3);
		#2 x1=1'bx; y1=1'bx;
		#2 $display(x1, " ",y1, "   ", w3);
		#2 x1=1'bx; y1=1'bz;
		#2 $display(x1, " ",y1, "   ", w3);
		
		#2 x1=1'bz; y1=1'b0;
		#2 $display(x1, " ",y1, "   ", w3);
		#2 x1=1'bz; y1=1'b1;
		#2 $display(x1, " ",y1, "   ", w3);
		#2 x1=1'bz; y1=1'bx;
		#2 $display(x1, " ",y1, "   ", w3);
		#2 x1=1'bz; y1=1'bz;
		#2 $display(x1, " ",y1, "   ", w3);
		#2 $display("");
	end
endmodule

Exercise3_2

module exercise3_2(w, x, y, z, out1, out2, out3, out4);
	input w, x, y, z;
	output out1, out2, out3, out4;
	wire wNot, xNot, yNot, zNot, and1, and2, and3, and4, and5, and6;
	
	not U1(wNot, w);
	not U2(xNot, x);
	not U3(yNot, y);
	not U4(zNot, z);
	
	//1000
	buf U5(out1, x);
	
	//0100
	and U6(and1, x, z);
	and U7(and2, x, y);
	or U8(out2, and1, and2);
	
	//0010
	and U9(and3, yNot, zNot);
	and U10(and4, y, z);
	or U11(out3, and3, and4);
	
	//0001
	buf U14(out4, zNot);
	
endmodule

module start3_2;
	wire o1, o2, o3, o4;
	reg w1, x1, y1, z1;
	
	exercise3_2 start3_2(w1, x1, y1, z1, o1, o2, o3, o4);
	initial begin
		w1=1'bx; x1=1'bx; y1=1'bx; z1=1'bx;
		#300 $finish;
	end
	
	initial begin
		#2 $display("BCD to 9's Complement Truth Table: ");
		#2 $display("--BCD--", "  --9's Comp--");
		#2 $display("w", " ", "x", " ", "y", " ", "z", "   ", "Q1", " ", "Q2", " ", "Q3", " ", "Q4");
		#2 $display(w1, " ", x1, " ", y1, " ", z1, "   ", o1, "  ", o2, "  ", o3, "  ", o4);
		#2 w1=1'bx; x1=1'bx; y1=1'bx; z1=1'bx;
		#2 $display(w1, " ", x1, " ", y1, " ", z1, "   ", o1, "  ", o2, "  ", o3, "  ", o4);
		#2 w1=1'bx; x1=1'bx; y1=1'bx; z1=1'bx;
		#2 $display(w1, " ", x1, " ", y1, " ", z1, "   ", o1, "  ", o2, "  ", o3, "  ", o4);
		#2 w1=1'bx; x1=1'bx; y1=1'bx; z1=1'bx;
		#2 $display(w1, " ", x1, " ", y1, " ", z1, "   ", o1, "  ", o2, "  ", o3, "  ", o4);
		#2 w1=1'bx; x1=1'bx; y1=1'bx; z1=1'bx;
		#2 $display(w1, " ", x1, " ", y1, " ", z1, "   ", o1, "  ", o2, "  ", o3, "  ", o4);
		#2 w1=1'bx; x1=1'bx; y1=1'bx; z1=1'bx;
		#2 $display(w1, " ", x1, " ", y1, " ", z1, "   ", o1, "  ", o2, "  ", o3, "  ", o4);
		#2 w1=1'bx; x1=1'bx; y1=1'bx; z1=1'bx;
		#2 $display(w1, " ", x1, " ", y1, " ", z1, "   ", o1, "  ", o2, "  ", o3, "  ", o4);
		#2 w1=1'bx; x1=1'bx; y1=1'bx; z1=1'bx;
		#2 $display(w1, " ", x1, " ", y1, " ", z1, "   ", o1, "  ", o2, "  ", o3, "  ", o4);
		#2 w1=1'bx; x1=1'bx; y1=1'bx; z1=1'bx;
		#2 $display(w1, " ", x1, " ", y1, " ", z1, "   ", o1, "  ", o2, "  ", o3, "  ", o4);
		#2 w1=1'b1; x1=1'b0; y1=1'b0; z1=1'b1;
		#2 $display(w1, " ", x1, " ", y1, " ", z1, "   ", o1, "  ", o2, "  ", o3, "  ", o4);
		#2 w1=1'b1; x1=1'b0; y1=1'b1; z1=1'b0;
		#2 $display(w1, " ", x1, " ", y1, " ", z1, "   ", o1, "  ", o2, "  ", o3, "  ", o4);
		#2 w1=1'b1; x1=1'b0; y1=1'b1; z1=1'b1;
		#2 $display(w1, " ", x1, " ", y1, " ", z1, "   ", o1, "  ", o2, "  ", o3, "  ", o4);
		#2 w1=1'b1; x1=1'b1; y1=1'b0; z1=1'b0;
		#2 $display(w1, " ", x1, " ", y1, " ", z1, "   ", o1, "  ", o2, "  ", o3, "  ", o4);
		#2 w1=1'b1; x1=1'b1; y1=1'b0; z1=1'b1;
		#2 $display(w1, " ", x1, " ", y1, " ", z1, "   ", o1, "  ", o2, "  ", o3, "  ", o4);
		#2 w1=1'b1; x1=1'b1; y1=1'b1; z1=1'b0;
		#2 $display(w1, " ", x1, " ", y1, " ", z1, "   ", o1, "  ", o2, "  ", o3, "  ", o4);
		#2 w1=1'b1; x1=1'b1; y1=1'b1; z1=1'b1;
		#2 $display(w1, " ", x1, " ", y1, " ", z1, "   ", o1, "  ", o2, "  ", o3, "  ", o4);
		#2 $display(" ");
	end
endmodule

Exercise3_3

//VERILOG FOR 2-BIT BY 2-BIT MULTIPLIER USING HALF ADDERS
module exercise3_3(a0,a1,b0,b1,p0,p1,p2,p3);
	input 		a0,a1,b0,b1;
	output 		p0,p1,p2,p3;
	wire 		and2,and3,and4,andd1;
	and		A1(p0,a0,b0), A2(and2,a1,b0), A3(and3,a0,b1), A4(and4,a1,b1);
	xor		X1(p1,and2,and3), X2(p2,andd1,and4);
	and		AA1(andd1,and2,and3), AA2(p3, andd1, and4);
endmodule

module testEx3_3;
	wire 	o1,o2,o3,o4;
	reg	ia1,ia2,ib1,ib2;

	exercise3_3	testEx3_3(ia1,ia2,ib1,ib2,o1,o2,o3,o4);

	initial begin
		#2 $display("a0 a1 b0 b1     product");
		ia1=1'b0;ia2=1'b0;ib1=1'b0;ib2=1'b0;	//0
		#100 $finish;
	end

	initial begin
		#2 $display(ia1,"  ",ia2,"  ",ib1,"  ",ib2, "      ",o1,o2,o3,o4);
		#2 ia1=1'b0;ia2=1'b0;ib1=1'b0;ib2=1'b1;
		#2 $display(ia1,"  ",ia2,"  ",ib1,"  ",ib2, "      ",o1,o2,o3,o4);
		#2 ia1=1'b0;ia2=1'b0;ib1=1'b1;ib2=1'b0;
		#2 $display(ia1,"  ",ia2,"  ",ib1,"  ",ib2, "      ",o1,o2,o3,o4);
		#2 ia1=1'b0;ia2=1'b0;ib1=1'b1;ib2=1'b1;
		#2 $display(ia1,"  ",ia2,"  ",ib1,"  ",ib2, "      ",o1,o2,o3,o4);
		#2 ia1=1'b0;ia2=1'b1;ib1=1'b0;ib2=1'b0;
		#2 $display(ia1,"  ",ia2,"  ",ib1,"  ",ib2, "      ",o1,o2,o3,o4);
		#2 ia1=1'b0;ia2=1'b1;ib1=1'b0;ib2=1'b1;
		#2 $display(ia1,"  ",ia2,"  ",ib1,"  ",ib2, "      ",o1,o2,o3,o4);
		#2 ia1=1'b0;ia2=1'b1;ib1=1'b1;ib2=1'b0;
		#2 $display(ia1,"  ",ia2,"  ",ib1,"  ",ib2, "      ",o1,o2,o3,o4);
		#2 ia1=1'b0;ia2=1'b1;ib1=1'b1;ib2=1'b1;
		#2 $display(ia1,"  ",ia2,"  ",ib1,"  ",ib2, "      ",o1,o2,o3,o4);
		#2 ia1=1'b1;ia2=1'b0;ib1=1'b0;ib2=1'b0;
		#2 $display(ia1,"  ",ia2,"  ",ib1,"  ",ib2, "      ",o1,o2,o3,o4);
		#2 ia1=1'b1;ia2=1'b0;ib1=1'b0;ib2=1'b1;
		#2 $display(ia1,"  ",ia2,"  ",ib1,"  ",ib2, "      ",o1,o2,o3,o4);
		#2 ia1=1'b1;ia2=1'b0;ib1=1'b1;ib2=1'b0;
		#2 $display(ia1,"  ",ia2,"  ",ib1,"  ",ib2, "      ",o1,o2,o3,o4);
		#2 ia1=1'b1;ia2=1'b0;ib1=1'b1;ib2=1'b1;
		#2 $display(ia1,"  ",ia2,"  ",ib1,"  ",ib2, "      ",o1,o2,o3,o4);
		#2 ia1=1'b1;ia2=1'b1;ib1=1'b0;ib2=1'b0;
		#2 $display(ia1,"  ",ia2,"  ",ib1,"  ",ib2, "      ",o1,o2,o3,o4);
		#2 ia1=1'b1;ia2=1'b1;ib1=1'b0;ib2=1'b1;
		#2 $display(ia1,"  ",ia2,"  ",ib1,"  ",ib2, "      ",o1,o2,o3,o4);
		#2 ia1=1'b1;ia2=1'b1;ib1=1'b1;ib2=1'b0;
		#2 $display(ia1,"  ",ia2,"  ",ib1,"  ",ib2, "      ",o1,o2,o3,o4);
		#2 ia1=1'b1;ia2=1'b1;ib1=1'b1;ib2=1'b1;
		#2 $display(ia1,"  ",ia2,"  ",ib1,"  ",ib2, "      ",o1,o2,o3,o4);
	end
endmodule

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